US-20260127120-A1 - SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICES WITH EXTENDED HIGH-BANDWIDTH MEMORY (HBM) OFFSETS

Abstract

The subject technology is directed to systems and methods for semiconductor devices with extended high-bandwidth memory (HBM) offsets. In a specific embodiment, the subject technology provides an apparatus that includes a circuit comprising a first connector and a second connector. The circuit is configured to send a first signal using the first connector to indicate a first selection. The apparatus further includes a first memory device comprising a first selector and a third connector and a fourth connector. The first selector is configured to couple the third connector to the second connector based on the first signal. The one or more connectors of the first memory devices cover a broad distance to ensure robust connectivity between the circuit and the first memory device. There are other embodiments as well.

Inventors

• Anwar Ali
• Deepam Trivedi
• Ho-Hsin Yeh

Assignees

• AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . An apparatus comprising: a circuit comprising a first connector and a second connector, the second connector being positioned at a first location, the circuit being configured to send a first signal using the first connector to indicate a first selection, the first selection being based on a spatial proximity between the first connector and the second connector; an interposer comprising a second interconnect; and a first memory device comprising a first selector, a third connector, and a fourth connector, the first memory device being positioned on the interposer at an offset from the circuit, wherein the first selector is configured to couple the third connector to the second connector through the second interconnect based on the first signal.
2. 2 . The apparatus of claim 1 , wherein the third connector is positioned closer to the first location than the fourth connector.
3. 3 . The apparatus of claim 1 , wherein the first selector comprises a multiplexor.
4. 4 . The apparatus of claim 1 , wherein the circuit comprises an application-specific integrated circuit.
5. 5 . The apparatus of claim 1 , wherein the first memory device comprises a high bandwidth memory.
6. 6 . The apparatus of claim 1 , wherein the interposer comprises a first interconnect, and wherein the first selector is coupled to the first connector through the first interconnect.
7. 7 . The apparatus of claim 1 , further comprising a second memory device, wherein the circuit further comprises a fifth connector and a sixth connector, the sixth connector being positioned at a second location, the circuit being configured to send a second signal using the fifth connector to indicate a second selection.
8. 8 . The apparatus of claim 7 , wherein the second memory device comprises a second selector and a seventh connector and an eighth connector, the second selector being configured to couple the seventh connector to the sixth connector based on the second signal.
9. 9 . The apparatus of claim 8 , wherein the seventh connector is positioned closer to the second location than the eighth connector.
10. 10 . The apparatus of claim 1 , further comprising a buffer die coupled between the first memory device and the interposer.
11. 11 . The apparatus of claim 10 , wherein the buffer die is configured to convert a memory protocol to an interposer interconnect compatible protocol.
12. 12 . An apparatus comprising: a circuit comprising a first connector and a second connector, the second connector being positioned at a first location, the circuit being configured to send a first signal using the first connector to indicate a first selection; an interposer comprising a first interconnect and a second interconnect; and a first memory device comprising a first selector, a third connector, and a fourth connector, the first memory device being positioned on the interposer at an offset from the circuit, wherein the first selector is coupled to the first connector through the first interconnect, and wherein the first selector is configured to couple the third connector to the second connector through the second interconnect based on the first signal, the third connector being positioned closer to the first location than the fourth connector.
13. 13 . The apparatus of claim 12 , wherein the first selector comprises a multiplexor.
14. 14 . The apparatus of claim 12 , wherein the circuit comprises an application-specific integrated circuit.
15. 15 . The apparatus of claim 12 , wherein the first memory device comprises a high bandwidth memory.
16. 16 . The apparatus of claim 12 , wherein the first selection is based on a spatial proximity between the first connector and the second connector.
17. 17 . The apparatus of claim 12 , further comprising a buffer die coupled between the first memory device and the interposer.
18. 18 . An apparatus comprising: a circuit comprising a first connector, a second connector, a third connector, and a fourth connector, the second connector being positioned at a first location, the fourth connector being positioned at a second location, the circuit being configured to send a first signal using the first connector to indicate a first selection and to send a second signal using the third connector to indicate a second selection; an interposer comprising a first interconnect; a first memory device comprising a first selector, a fifth connector, and a sixth connector, the first memory device being positioned on the interposer at an offset from the circuit, wherein the first selector is configured to couple the fifth connector to the second connector through the first interconnect based on the first signal; and a second memory device comprising a second selector, a seventh connector, and an eighth connector, wherein the second selector is configured to couple the seventh connector to the fourth connector based on the second signal.
19. 19 . The apparatus of claim 18 , wherein the fifth connector is positioned closer to the first location than the sixth connector.
20. 20 . The apparatus of claim 18 , wherein the seventh connector is positioned closer to the second location than the eighth connector.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application is a continuation of U.S. patent application Ser. No. 18/474,384, filed Sep. 26, 2023, and published on Dec. 5, 2024, under Publication No. 2024-0403240. U.S. patent application Ser. No. 18/474,384 claims the benefit of U.S. Provisional Patent Application No. 63/505,934, filed Jun. 2, 2023. These patent applications are incorporated herein by reference in their entirety for all purposes. FIELD OF INVENTION The subject technology is directed to systems and methods for semiconductor devices with extended high-bandwidth memory (HBM) offsets. BACKGROUND OF THE INVENTION Over the past decades, the realm of semiconductor integration has witnessed considerable advancements, particularly in the strategic positioning and interconnection of integrated circuit (IC) devices. Various approaches involve placing IC devices side-by-side on an interposer, which facilitates high-density connections between IC components, allowing for efficient and compact designs. For instance, in a 2.5D interposer configuration, one or more high-bandwidth memories (HBMs) can be connected to an application-specific IC (ASIC) in accordance with a set of predetermined routing rules. For example, HBM refers to a memory that provide a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM), and it is standardized stacked memory technology that provides very wide channels for data, both within the stack and between the memory and logic. Due to disparities in IC dimensions, one or more HBMs cannot be in alignment with the ASIC and need to be offset from their designated pins on the ASIC. However, it remains challenging to expand these offsets to accommodate various IC size variations and to ensure efficient signal transmission. Various approaches for increasing HBM offsets have been explored, but they have proven to be insufficient. It is important to recognize the need for new and improved semiconductor devices with extended HBM offsets. BRIEF DESCRIPTION OF THE DRAWINGS A further understanding of the nature and advantages of particular embodiments may be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. FIG. 1 is a simplified diagram illustrating a semiconductor device characterized by an integration scheme according to embodiments of the subject technology. FIG. 2 is a simplified diagram illustrating a cross-section view of a semiconductor device characterized by an integration scheme according to embodiments of the subject technology. FIG. 3 is a simplified diagram illustrating a semiconductor device characterized by an integration scheme according to embodiments of the subject technology. FIG. 4 is a simplified diagram illustrating a semiconductor device characterized by an integration scheme according to embodiments of the subject technology. FIG. 5 is a simplified diagram illustrating a cross-section view of a semiconductor device characterized by an integration scheme according to embodiments of the subject technology. FIG. 6 is a simplified diagram illustrating a semiconductor device characterized by an integration scheme according to embodiments of the subject technology. FIG. 7 is a simplified diagram illustrating a cross-section view of a semiconductor device characterized by an integration scheme according to embodiments of the subject technology. DETAILED DESCRIPTION OF THE INVENTION The subject technology is directed to systems and methods for semiconductor devices with extended high-bandwidth memory (HBM) offsets. In an embodiment, the subject technology provides an apparatus that includes a circuit comprising a first connector and a second connector. The circuit is configured to send a first signal using the first connector to indicate a first selection. The apparatus further includes a first memory device comprising a first selector and a third connector and a fourth connector. The first selector is configured to couple the third connector to the second connector based on the first signal. The one or more connectors of the first memory devices cover a broad distance to ensure robust connectivity between the circuit and the first memory device. There are other embodiments as well. Some approaches for implementing semiconductor integration involve connecting one or more HBM to an ASIC through interconnects in interposer. For instance, an HBM can be centered to its associated physical layer (PHY) circuit (e.g., transceiver) within the ASIC to ensure minimized routing distances and optimal signal transmission. This, however, is not always practical