US-20260127123-A1 - IN-MEMORY PROCESSING CHIP

US20260127123A1US 20260127123 A1US20260127123 A1US 20260127123A1US-20260127123-A1

Abstract

The present disclosure provides an in-memory processing chip, which may include at least an interface circuit, a memory circuit, and a computing unit. A first transmission path exists between the interface circuit and the memory circuit; a second transmission path exists between the memory circuit and the computing unit; and a third transmission path exists between the interface circuit and the computing unit, and the third transmission path and the first transmission path are independent of each other.

Inventors

Kanyu Cao
Huayao Tu
Yanzhe TANG
Lin Zhang
Hongwen Li
Enpeng Gao

Assignees

CXMT Corporation

Dates

Publication Date: 20260507
Application Date: 20251218
Priority Date: 20241009

Claims (12)

1 . An in-memory processing chip, comprising an interface circuit, a memory circuit, and a computing unit; a first transmission path existing between the interface circuit and the memory circuit; a second transmission path existing between the memory circuit and the computing unit; and a third transmission path existing between the interface circuit and the computing unit, and the third transmission path and the first transmission path being independent of each other.
2 . The in-memory processing chip according to claim 1 , comprising a plurality of memory circuits and a plurality of computing units, each of the computing units corresponding to at least one memory circuit, different memory circuits each having a corresponding first transmission path and a corresponding second transmission path, and different memory circuits each being connected to the interface circuit through the corresponding first transmission path.
3 . The in-memory processing chip according to claim 1 , wherein the first transmission path is at least configured to transmit model data, the second transmission path is at least configured to transmit model data, the third transmission path is at least configured to transmit initial data and target data, and the computing unit performs computing processing on the initial data based on the model data to obtain the target data.
4 . The in-memory processing chip according to claim 3 , wherein the first transmission path is further configured to transmit the initial data and the target data, and the second transmission path is further configured to transmit the initial data and the target data.
5 . The in-memory processing chip according to claim 4 , wherein bandwidths of the first transmission path and the second transmission path are each greater than a bandwidth of the third transmission path, and a priority of the third transmission path in transmitting the initial data and the target data is higher than priorities of the first transmission path and the second transmission path.
6 . The in-memory processing chip according to claim 1 , further comprising a gating circuit, the memory circuit being connected to the first transmission path or the second transmission path through the gating circuit.
7 . The in-memory processing chip according to claim 6 , wherein the gating circuit is further configured to record refresh information of a corresponding memory circuit, and is configured to send the recorded refresh information to the interface circuit before the interface circuit is disconnected from the memory circuit or after the interface circuit is reconnected to the memory circuit.
8 . The in-memory processing chip according to claim 6 , further comprising a memory controller disposed between a corresponding memory circuit and a corresponding gating circuit, or disposed between a corresponding gating circuit and the computing unit, and the memory controller being at least configured to read data in the memory circuit.
9 . The in-memory processing chip according to claim 6 , further comprising a mode control circuit configured to control the memory circuit to be connected to the first transmission path, or control the memory circuit to be connected to the second transmission path.
10 . The in-memory processing chip according to claim 9 , wherein the mode control circuit is further configured to connect or disconnect the third transmission path.
11 . The in-memory processing chip according to claim 9 , wherein the mode control circuit is in a region in which the interface circuit is located.
12 . The in-memory processing chip according to claim 1 , wherein a total bandwidth between the memory circuit and the computing unit in the in-memory processing chip is greater than a bandwidth between the in-memory processing chip and an external processor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present disclosure is a continuation application of International Application No. PCT/CN2025/102310, filed on Jun. 20, 2025, which is based on and claims priority of the Chinese Patent Application No. 202411396760.9, filed with the China National Intellectual Property Administration on Oct. 9, 2024 and entitled “IN-MEMORY PROCESSING CHIP”. The above-referenced application is incorporated herein by reference in its entirety. TECHNICAL FIELD Embodiments of this application relate to the field of semiconductors, and in particular to an in-memory processing chip. BACKGROUND With continuous development of artificial intelligence and big data, a demand for computing power in various application scenarios continuously increases. However, a mainstream computing architecture adopts a Von Neumann architecture that separates storage and computing, and a bandwidth increase speed of a memory has lagged far behind a computing power increase speed of a processor. Therefore, a memory wall problem in which actual computing power of a computing system is limited due to insufficient bandwidth exists. An existing in-memory processing chip is implemented by replacing some memory units in a memory chip with computing units, which may not change an encapsulation manner of an entire chip, but a problem of capacity loss and low computing power exists. SUMMARY Embodiments of this application provide a new architecture of an in-memory processing chip. According to some embodiments of this application, the embodiments of this application provide an in-memory processing chip, including an interface circuit, a memory circuit, and a computing unit. A first transmission path exists between the interface circuit and the memory circuit; a second transmission path exists between the memory circuit and the computing unit; and a third transmission path exists between the interface circuit and the computing unit, and the third transmission path and the first transmission path are independent of each other. BRIEF DESCRIPTION OF DRAWINGS One or more embodiments are exemplified with the figures in the accompanying drawings corresponding to the one or more embodiments. These example descriptions are not intended to limit the embodiments, and unless specifically stated, no scale limitations are constituted by the figures in the accompanying drawings. FIG. 1 to FIG. 7 are schematic diagrams of a structure of an in-memory processing chip according to embodiments of this application; and FIG. 8 is a schematic diagram of a structure of a computing system according to an embodiment of this application. DESCRIPTION OF EMBODIMENTS Embodiments of this application are described in detail below with reference to the accompanying drawings. However, it may be understood by a person of ordinary skill in the art that in the embodiments of this application, many technical details are provided to enable readers to better understand this application. However, the technical solutions claimed in this application may be implemented even without these technical details and various changes and modifications made based on the following embodiments. FIG. 1 to FIG. 7 are schematic diagrams of a structure of an in-memory processing chip according to embodiments of this application. Referring to FIG. 1, the in-memory processing chip includes an interface circuit 11, a memory circuit 12, and a computing unit 13. A first transmission path TR1 exists between the interface circuit 11 and the memory circuit 12, a second transmission path TR2 exists between the memory circuit 12 and the computing unit 13, a third transmission path TR3 exists between the interface circuit 11 and the computing unit 13, and the third transmission path TR3 and the first transmission path TR1 are independent of each other. In the present disclosure, the computing unit 13 is separately connected to the interface circuit 11 and the memory circuit 12, and the first transmission path TR1, the second transmission path TR2, and the third transmission path TR3 may all be configured for data transmission. That the third transmission path TR3 and the first transmission path TR1 are independent of each other means that there is no inevitable association between an available state of the first transmission path TR1 and an available state of the third transmission path TR3. Both may be in an available state or an unavailable state simultaneously, or one may be in an available state while the other may be in an unavailable state, which depends on a corresponding control signal. An available state of each transmission path is related to at least two factors: 1. A connection or disconnection within the transmission path, for example, a connection or disconnection of an internal driver. If the transmission path is disconnected, the transmission path is unavailable. 2. Whether the transmission path is in data communication with a data input circuit or a data output circuit. If