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US-20260127124-A1 - INTERFACE SYSTEM AND REMOTE I2C SLAVE DEVICE DATA WRITING METHOD

US20260127124A1US 20260127124 A1US20260127124 A1US 20260127124A1US-20260127124-A1

Abstract

The present disclosure provides an interface system, comprising a master controller, an interface module, a functional module, and a remote I2C slave device; the master controller is connected to the interface module; the interface module is connected to the functional module, and the functional module is connected to the remote I2C slave device. The present disclosure is applicable for long-distance data transmission, with a high data transfer speed.

Inventors

  • Yuanlong Wang
  • Hui Wang

Assignees

  • NOREL SYSTEMS LIMITED

Dates

Publication Date
20260507
Application Date
20251229
Priority Date
20231206

Claims (12)

  1. 1 . A method for writing data to a remote I2C slave device of an interface system, wherein the interface system is configured to write data to the remote I2C slave device, the method comprising: providing the interface system, comprising a master controller, an interface module, a functional module and the remote I2C slave device, wherein the master controller is connected to the interface module, the interface module is connected to the functional module, and the functional module is connected to the remote I2C slave device; the master controller sending a write command packet to the interface module, and upon receiving the write command packet, the interface module forwarding the write command packet to the functional module, wherein the write command packet contains a plurality of write commands, and the functional module receives the write command packet and executes the plurality of write commands contained therein, wherein a method for executing each write command is as follows: the functional module sending an I2C START to the remote I2C slave device, then the functional module sending a remote I2C address byte to the remote I2C slave device, followed by the functional module sending the write command to the remote I2C slave device; for each byte sent by the functional module to the remote I2C slave device, the functional module receiving an I2C acknowledgment bit from the remote I2C slave device and determining an execution result of the write command, the functional module returning a write status packet to the interface module, comprising: when the execution result of each write command in the write command packet is success, the functional module returning a write status packet with status information indicating success to the interface module; when the execution result of at least one write command in the write command packet is failure, the functional module returning a write status packet with status information indicating failure to the interface module; and the interface module returning the status information of the write status packet to the master controller.
  2. 2 . The method according to claim 1 , wherein the functional module receives the write command packet and executes the write commands contained therein; and when a execution result of a write command is failure, the functional module stops executing subsequent write commands and returns a write status packet with status information indicating failure to the interface module.
  3. 3 . The method according to claim 1 , wherein the master controller is an I2C master controller, and the interface module is an I2C interface module; the I2C master controller is connected to the I2C interface module via an I2C clock line and an I2C data line; the I2C master controller initiates an I2C write operation to send the write command packet to the I2C interface module; and upon receiving the write command packet, the I2C interface module pulls down a leve of the I2C clock line and forwards the write command packet to the functional module; the functional module returns the write status packet to the I2C interface module, and the I2C interface module then relays the status information of the write status packet back to the I2C master controller, comprising: when the I2C interface module receives the write status packet and the status information of the write status packet indicates success, the I2C interface module stops pulling down the level of the I2C clock line and returns an I2C ACK to the I2C master controller; and when the I2C interface module receives the write status packet and the status information of the write status packet indicates failure, the I2C interface module stops pulling down the level of the I2C clock line and returns an I2C NAK to the I2C master controller.
  4. 4 . The method according to claim 1 , wherein the master controller is an I2C master controller, and the interface module is an I2C interface module; the I2C master controller is connected to the I2C interface module via an I2C clock line and an I2C data line; the I2C master controller initiates an I2C write operation to send the write command packet to the I2C interface module; and upon receiving the write command packet, the I2C interface mode forwards the write command packet to the functional module; the functional module returns the write status packet to the I2C interface module, and the I2C interface module then relays the status information of the write status packet back to the I2C master controller, comprising: after the I2C interface module receives the write command packet, if a subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives the write status packet returned by the functional module with status information thereof indicating success, the I2C interface module proceeding to accept the subsequent I2C write operation initiated by the I2C master controller; if the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, and the I2C interface module receives the write status packet returned by the functional module to the I2C interface module with status information thereof indicating failure, then the I2C interface module returning an I2C NAK to the I2C master controller; and if the subsequent I2C operation initiated by the I2C master controller is an I2C read operation, and the I2C interface module receives the write status packet returned by the functional module to the I2C interface module, then the I2C interface module returning the status information of the write status packet to the I2C master controller.
  5. 5 . The method according to claim 1 , wherein the master controller is an SPI master controller, the interface module is an SPI interface module, and the SPI master controller is connected to the SPI interface module via a SPI_CK signal line, a SPI_MOSI signal line and a SPI_MISO signal line; the SPI master controller generates a clock edge on the SPI_CK signal line and sends the write command packet to the SPI interface module via the SPI_MOSI signal line; the write command packet begins with a first identifier; and upon receiving the write command packet from SPI_MOSI, the SPI interface module forwards the write command packet to the functional module; and the functional module returns the write status packet to the SPI interface module, and the SPI interface module returns the status information of the write status packet to the SPI master controller, comprising: upon receiving the write status packet, when the SPI master controller generates a clock edge on SPI_CK, the SPI interface module sending a write feedback packet to the SPI master controller via the SPI_MISO signal line, wherein the write feedback packet begins with a second identifier and contains the status information comprised in the write status packet.
  6. 6 . The method according to claim 5 , wherein the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet via the SPI_MISO signal line; and if the SPI interface module does not receive the write status packet, the SPI interface module sends data unrecognizable as the write feedback packet to the SPI master controller via the SPI_MISO signal line.
  7. 7 . The method according to claim 5 , wherein the SPI master controller generates a clock edge on the SPI_CK signal line and sends the write command packet to the SPI interface module via the SPI_MOSI signal line; and then, the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet via the SPI_MISO signal line, and after sending the write feedback packet via SPI_MISO, the SPI interface module can continue to receive subsequent command packets.
  8. 8 . The method according to claim 5 , wherein the write feedback packet is divided into a write success feedback packet and a write failure feedback packet; the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet through the SPI_MISO signal line, when the SPI interface module receives the write status packet and the status information contained in the write status packet indicates success, the SPI interface module sends the write success feedback packet through the SPI_MISO signal line, and the write success feedback packet begins with a third identifier; and when the SPI interface module receives the write status packet and the status information contained in the write status packet indicates failure, the SPI interface module sends the write failure feedback packet through the SPI_MISO signal line, and the write failure feedback packet begins with a fourth identifier.
  9. 9 . The method according to claim 1 , wherein the functional module comprises a remote I2C address register, and an I2C address contained in the remote I2C address byte sent by the functional module to the remote I2C slave device is a remote I2C address stored in the remote I2C address register.
  10. 10 . The method according to claim 1 , wherein the write command packet contains a remote I2C address, and the I2C address contained in the remote I2C address byte sent by the functional module to the remote I2C slave device is the remote I2C address contained in the write command packet.
  11. 11 . The method according to claim 10 , wherein the functional module comprises a remote I2C address register and a remote I2C address selection module, and the I2C address contained in the remote I2C address byte sent by the functional module to the remote I2C slave device, as instructed by the remote I2C address selection module, is derived from either the remote I2C address stored in the remote I2C address register or the remote I2C address contained in the write command packet.
  12. 12 . The method according to claim 1 , wherein the plurality of write commands in the write command packet each contain a remote I2C address, and the remote I2C address contained in the remote I2C address byte sent by the functional module to the remote I2C slave device is derived from the remote I2C address contained in each respective write command.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of International Patent Application No. PCT/CN 2024/119278, filed on Sep. 18, 2024, which itself claims priority to and benefit of Chinese Patent Application No. 202311669609.3 filed on Dec. 6, 2023 in the State Intellectual Property Office of P. R. China. The disclosure of each of the above applications is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the field of communication technologies, particularly to an interface system and a remote I2C slave device data writing method. BACKGROUND The I2C bus is a simple, bidirectional serial bus developed by Philips. Devices interconnected via the I2C bus are called I2C devices, and the interface through which an I2C device is connected to the I2C bus is called an I2C interface. The I2C bus has become a de facto international standard, and the design specifications of the I2C bus and its protocol (referred to as the standard I2C specification) are typically based on the descriptions in the document THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000. The I2C interface includes an I2C clock line (usually named SCL) and an I2C data line (usually named SDA). The I2C master controller is connected to one or more I2C slave devices via the I2C clock line and data line. The I2C master controller drives the I2C clock line, initiates I2C write or read operations, and determines whether data transmission is success through acknowledgment bits. Bit errors on the bus caused by signal interference or other factors cannot be detected by the I2C slave devices. The electrical characteristics of the I2C interface require devices participating in I2C communication to share a common ground; otherwise, transmission is impossible. Therefore, I2C communication is unapplicable for application scenarios with long transmission distances or significant signal interference. To address this issue, devices for forwarding I2C data are often added to the I2C bus, but introducing forwarding devices introduces new problems: The I2C communication mechanism requires the I2C master controller to receive an acknowledgment bit from the I2C slave device for every byte sent. A low-level acknowledgment bit is an I2C ACK, while a high-level one is an I2C NAK. In the prior art, every byte sent by the I2C master controller is transmitted to the final data-receiving module (referred to as the functional module in the present disclosure), and the acknowledgment bit is generated by the functional module and sent back to the I2C master controller. The slow acknowledgment speed of the transmission system results in slow transmission speeds. SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus that uses only four wires on the chip's pins, saving pin resources and providing convenience for PCB layout. SPI typically consists of four signal lines: SPI_CSN, SPI_CK, SPI_MOSI, and SPI_MISO. The SPI master controller is connected to the SPI interface module through these four signal lines, with the master controller acting as the SPI master device and the interface module as the SPI slave device. The master controller drives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines, while the interface module receives these signals. Conversely, the interface module drives the SPI_MISO signal line, which the master controller receives. The interface module samples the data driven by the master controller on the SPI_MOSI signal line at the rising or falling clock edge of SPI_CK, while the master controller samples the data driven by the interface module on the SPI_MISO signal line at the same clock edges. In the SPI protocol, the master controller generates the clock edges on the SPI_CK signal line, and both the master controller and interface module sample data on SPI_MISO and SPI_MOSI at these edges, enabling bidirectional data transfer between them. The SPI_CSN signal line serves as the select signal; data transmission occurs only when SPI_CSN is low. One master controller can connect to a plurality of interface modules (i.e., one master to a plurality of slaves), sharing SPI_CK, SPI_MOSI, and SPI_MISO signal lines. However, each interface module has its own SPI_CSN input. When an interface module's SPI_CSN is high, it does not drive the SPI_MISO line (its driver outputs a Hi-Z state). Only when SPI_CSN is low does the interface module drive SPI_MISO. When a plurality of interface modules are connected to one master, only one module's SPI_CSN is low at any time, preventing conflicts from simultaneous driving of SPI_MISO by a plurality of modules. When an SPI master controller is connected to only one SPI interface module, this SPI interface module can drive the SPI_MISO signal line at any time without causing conflicts. In this case, there may be no SPI_CSN signal line between the SPI master controller and the SPI interface module. That is, when an SPI m