US-20260127128-A1 - COMPENSATING DC LOSS IN USB 2.0 HIGH SPEED APPLICATIONS

US20260127128A1US 20260127128 A1US20260127128 A1US 20260127128A1US-20260127128-A1

Abstract

In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.

Inventors

Yonghui Tang
Yanli Fan

Assignees

TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date: 20260507
Application Date: 20260105

Claims (20)

1 . A method, comprising: detecting a non-transition period of a signal on a positive data line and a negative data line; in response to detecting the non-transition period, injecting a current into one of the positive data line or the negative data line; and in response to not detecting the non-transition period, ceasing the injection of the current.
2 . The method of claim 1 , wherein detecting the non-transition period comprises: detecting a rising edge of the signal on one of the data lines; and detecting a falling edge of the signal on the data line.
3 . The method of claim 2 , wherein the current is injected between the rising edge and the falling edge.
4 . The method of claim 2 , wherein injecting the current comprises: determining whether the rising edge is on the positive data line or the negative data line; in response to determining that the rising edge is on the positive data line, injecting the current into the positive data line; and in response to determining that the rising edge is on the negative data line, injecting the current into the negative data line.
5 . The method of claim 1 , wherein detecting the non-transition period comprises using a voltage threshold comparator to monitor a voltage difference between the positive and negative data lines.
6 . The method of claim 5 , wherein the voltage threshold comparator detects whether the voltage difference exceeds a threshold.
7 . The method of claim 1 , further comprising grounding the current in response to not detecting the non-transition period.
8 . The method of claim 1 , wherein the positive and negative data lines are of a Universal Serial Bus (USB) communication system.
9 . A system, comprising: detection circuitry configurable to detect a non-transition period of a signal transmitted through a positive data line and a negative data line; and current injection circuitry configurable to: in response to detecting the non-transition period, inject a current into one of the positive data line or the negative data line; and in response to not detecting the non-transition period, cease the injection of the current.
10 . The system of claim 9 , wherein to detect the non-transition period, the detection circuitry is configurable to: detect a rising edge of the signal on one of the data lines; and detect a falling edge of the signal on the data line.
11 . The system of claim 10 , wherein to inject the current, the current injection circuitry is configurable to inject the current between the rising edge and the falling edge.
12 . The system of claim 10 , wherein: the detection circuitry is configurable to determine whether the rising edge is on the positive data line or the negative data line; and the current injection circuitry is configurable to: in response to determining that the rising edge is on the positive data line, inject the current into the positive data line; and in response to determining that the rising edge is on the negative data line, inject the current into the negative data line.
13 . The system of claim 9 , wherein to detect the non-transition period, the detection circuitry comprises a voltage threshold comparator configurable to monitor a voltage difference between the positive and negative data lines.
14 . The system of claim 13 , wherein the voltage threshold comparator is configurable to detect whether the voltage difference exceeds a threshold.
15 . The system of claim 9 , wherein the current injection circuitry is configurable to ground the current in response to not detecting the non-transition period.
16 . The system of claim 9 , wherein the positive and negative data lines are of a Universal Serial Bus (USB) communication system.
17 . The system of claim 9 , wherein the detection circuitry comprises: a first voltage threshold comparator having a first input terminal coupled to the positive data line, a second input terminal coupled to the negative data line, and an output terminal; a second voltage threshold comparator having a first input terminal coupled to the positive data line, a second input terminal coupled to the negative data line, and an output terminal; a third voltage threshold comparator having a first input terminal coupled to the negative data line, a second input terminal coupled to the positive data line, and an output terminal; and a fourth voltage threshold comparator having a first input terminal coupled to the negative data line, a second input terminal coupled to the positive data line, and an output terminal.
18 . The system of claim 17 , wherein the detection circuitry further comprises: a first NOR gate having a first input terminal coupled to the output terminal of first voltage threshold comparator, a second input terminal coupled to the output terminal of the second voltage threshold comparator, and an output terminal; and a second NOR gate having a first input terminal coupled to the output terminal of third voltage threshold comparator, a second input terminal coupled to the output terminal of the fourth voltage threshold comparator, and an output terminal.
19 . The system of claim 18 , wherein the current injection circuitry comprises: a current source; a first switch having a first current terminal coupled to the current source, a second current terminal coupled to the positive data line, and a control terminal coupled to the output terminal of the first NOR gate; and a second switch having a first current terminal coupled to the current source, a second current terminal coupled to the negative data line, and a control terminal coupled to the output terminal of the second NOR gate.
20 . The system of claim 19 , wherein: the detection circuitry further comprises: a third NOR gate having a first input terminal coupled to the output terminal of first NOR gate, a second input terminal coupled to the output terminal of second NOR gate, and an output terminal; and the current injection circuitry further comprises: a third switch having a first current terminal coupled to the current source, a second current terminal coupled to ground, and a control terminal coupled to the output terminal of the third NOR gate.

Description

PRIORITY This application is a continuation of U.S. patent application Ser. No. 18/672,723, filed May 23, 2024, which is a continuation of U.S. patent application Ser. No. 17/968,978, filed Oct. 19, 2022, which is a continuation of U.S. patent application Ser. No. 16/915,751, filed Jun. 29, 2020, which is a continuation of U.S. patent application Ser. No. 15/967,883, filed May 1, 2018, which claims the benefit, under 35 U.S.C. § 119(e), of U.S. Provisional Patent Application No. 62/616,201, filed Jan. 11, 2018, all of which are incorporated herein by reference. TECHNICAL FIELD This disclosure generally relates to compensating direct current (“DC”) loss, and in particular compensating DC loss in a USB 2.0 system. BACKGROUND Many modern day applications (e.g., vehicle infotainment systems) use USB 2.0 data transmissions. Moreover, these USB 2.0 systems are becoming more complicated especially with the introduction of additional components (e.g., USB cable, PCB trace, signal switches, etc.) in USB 2.0 systems. However, the introduction of these additional components has led to a direct current (“DC”) loss in the data transmission with a shrinking eye height as these components introduce additional resistance to the data path. In certain situations, the DC loss causes the signal to fail the eye diagram compliance test for USB 2.0. Conventionally, USB 2.0 hubs attempt to alleviate this issue by repeating the signals between USB 2.0 host and device. However, these USB 2.0 hubs are intrusive as the hubs break the transmission line, require a large amount of power, and must understand and repeat the signal. Moreover, because of its uni-directional nature, USB 2.0 hubs may not fully support the USB On-The-Go and Embedded Host Supplement to the USB 2.0 Specification as this supplement provides for a host and device to interchange roles. SUMMARY OF PARTICULAR EMBODIMENTS This disclosure uses a transition detection mechanism to detect the start-stop of the data transition period. A current is injected into the “high” level signal during the non-transition period so as to raise the DC level of the “high” signal. It will help a failed communication, e.g., USB 2.0, system due to shrinking eye height pass the system eye diagram compliance test. The disclosure may present several technical advantages. Technical advantages of the DC loss compensation circuit may include a current-boosting system that is simple to implement, inherently power-efficient, and direction agnostic. Moreover, the DC loss compensation circuit may help maintain signal integrity for signals communicated between two components in a communication, e.g., USB 2.0, system. In addition, the DC loss compensation circuit provides flexibility to adjust the parameters to accommodate a wide range of system applications, including USB system applications. In addition, the DC loss compensation circuit may be compatible with the USB On-The-Go and Embedded Host Supplement to the USB 2.0 Specification. Other technical advantages of the present disclosure will be readily apparent to one skilled in the art from the following figures, descriptions, and claims. Moreover, while specific advantages have been enumerated above, various embodiments may include all, some, or none of the enumerated advantages. Moreover, the embodiments disclosed herein are only examples, and the scope of this disclosure is not limited to them. Particular embodiments may include all, some, or none of the components, elements, features, functions, operations, or steps of the embodiments disclosed above. Embodiments according to the invention are in particular disclosed in the attached claims, wherein any feature mentioned in one claim category, e.g. method, can be claimed in another claim category, e.g. system, as well. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the disclosure may be implemented in certain parts, steps, and embodiments that will be described in detail in the following description and illustrated in the accompanying drawings in which like reference numerals indicate similar elements. It will be appreciated with the benefit of this disclosure that the steps illustrated in the accompanying figures may be performed in other than the recited order and that one or more of the steps disclosed may be optional. It will also be appreciated with the benefit of this disclosure that one or more components illustrated in the accompanying figures may be positioned in other than the disclosed arrangement and that one or more of the components illustrated may be optional. FIG. 1 illustrates an exemplary USB 2.0 system incorporating direct current (“DC”) loss compensation circuit 130. FIG. 2 illustrates an exemplary circuit diagram of a DC loss compensation circuit with a positive data line and a negative data line. FIG. 3 illustrates an example signal diagram for injecting current in either a positive data line or a negative data line by a DC loss compensation circuit. FIG. 4 illustrates an exam