US-20260127131-A1 - COMMUNICATION MODULE

US20260127131A1US 20260127131 A1US20260127131 A1US 20260127131A1US-20260127131-A1

Abstract

A communication module includes: an amplification control device connected to a main device to receive, from the main device, a main signal including a command signal, an address signal that identifies an address of at least one register included in an antenna switch and a band select switch, and a write data signal to be recorded in a register corresponding to the address and interpret the command signal; and the antenna switch and the band select switch connected to the amplification control device via a first signal line where a clock signal is transmitted and a second signal line where a data signal is transmitted.

Inventors

Kazuhiro Nakamuta

Assignees

MURATA MANUFACTURING CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251031
Priority Date: 20241106

Claims (14)

1 . A communication module comprising: a first sub-device connected to a main device; and at least one second sub-device not connected to the main device but connected to the first sub-device via a first signal line where a clock signal is transmitted, and via a second signal line where a data signal is transmitted, wherein the first sub-device is configured to: receive, from the main device, a main signal including a command signal, an address signal that identifies an address of at least one register included in at least one second sub-device, and a write data signal to be recorded in a register corresponding to the address, the address signal being a signal subsequent to the command signal and the write data signal being a signal subsequent to the address signal, interpret the command signal, generate a write instruction signal based on an interpretation result of the command signal after reception of the command signal and during reception of the main signal when information based on the data signal is written in any of the at least one second sub-device, generate the data signal based on the interpretation result of the command signal to each of the at least one second sub-device based on the address signal and the write data signal after reception of the command signal and during reception of the main signal, and supply the write instruction signal via the first signal line or the second signal line and the data signal via the second signal line to each of the at least one second sub-device after reception of the command signal and during reception of the main signal, and wherein each of the at least one second sub-device is configured to: determine whether the register corresponding to the address indicated by the address signal is included in the at least one second sub-device, and write the write data signal in the register when the register is included in the at least one second sub-device and the write instruction signal is supplied from the first sub-device.
2 . The communication module according to claim 1 , wherein the first sub-device is configured to generate the data signal including identification information based on a type of writing of the write data signal to the at least one register, the write instruction signal being included in a tail of the data signal as the identification information, and wherein each of the at least one second sub-device is configured to write the write data signal in the register based on the identification information.
3 . The communication module according to claim 2 , wherein the identification information is information indicating a data length of the data signal.
4 . The communication module according to claim 2 , wherein the identification information is information indicating a type of data included in the data signal.
5 . The communication module according to claim 4 , wherein the type of writing includes a writing type indicating that a predetermined bit of the register is not rewritten and part of the write data signal is written in the register, wherein the identification information indicates that the type of data included in the data signal is the write data signal or a mask signal indicating the predetermined bit not rewritten, and wherein each of the at least one second sub-device is configured to write part of the write data signal to the at least one register based on the write data signal and the mask signal.
6 . The communication module according to claim 4 , wherein the type of writing includes a writing type indicating that a first write data signal is written in a first register of the at least one second sub-device and a second write data signal is written in a second register of the at least one second sub-device, wherein the identification information is included in a tail of each of the first write data signal and the second write data signal, and wherein each of the at least one second sub-device is configured to write the first write data signal in the first register and the second write data signal in the second register based on the identification information.
7 . The communication module according to claim 1 , wherein the write instruction signal is the clock signal generated subsequently to the data signal.
8 . The communication module according to claim 1 , wherein the main signal includes the command signal indicating that information is read from the at least one register of the at least one second sub-device, and wherein the first sub-device is configured to: generate a read instruction signal based on the address signal when information stored in the at least one register is read from the at least one second sub-device based on the interpretation result of the command signal, supply the read instruction signal via the first signal line or via the second signal line to each of the at least one second sub-device, receive a read signal read from the register of any of the at least one second sub-device, and transmit the read signal to the main device.
9 . The communication module according to claim 8 , wherein the first sub-device is configured to: generate the read instruction signal including identification information based on a type of reading from the at least one register, and receive the read signal read from the at least one second sub-device based on the identification information.
10 . The communication module according to claim 9 , wherein the identification information is information indicating a data length of the read signal.
11 . The communication module according to claim 8 , wherein the main signal includes the command signal indicating that the at least one second sub-device is set in write mode or read mode, and wherein the first sub-device is configured to: generate a mode setting signal for setting the at least one second sub-device in write mode or read mode based on the interpretation result of the command signal, supply the mode setting signal via the first signal line or the second signal line to each of the at least one second sub-device, and receive a read signal read from the register of any of the at least one second sub-device set in read mode and supplied with the read instruction signal.
12 . The communication module according to claim 1 , wherein the first sub-device is an amplification control device configured to control a power amplifier circuit, and wherein the at least one second sub-device is an antenna switch configured to select a signal amplified by the power amplifier circuit and transmitted and received via an antenna, or a band select switch configured to select a wavelength of a signal transmitted and received via the antenna.
13 . The communication module according to claim 1 , wherein the first sub-device is configured to not write the write data signal in any of the at least one second sub-device when the main signal has an error.
14 . A communication module comprising: a first sub-device connected to a main device and configured to receive, from the main device, a main signal including a command signal and a device ID signal indicating a device ID for identifying a device, interpret the command signal, and have first device ID information allocated thereto; a second sub-device connected to the first sub-device via a first signal line where a clock signal is transmitted and via a second signal line where a data signal is transmitted to have second device ID information allocated thereto; and a third sub-device connected to the first sub-device via a third signal line where the clock signal is transmitted and via a fourth signal line where the data signal is transmitted to have third device ID information allocated thereto, wherein the first sub-device is configured to: determine whether the device ID signal included in the main signal matches the first device ID information the first sub-device has, determine whether the device ID signal included in the main signal matches the second device ID information or the third device ID information the first sub-device has, when the device ID signal included in the main signal matches the second device ID information the first sub-device has, generate a first sub-device control signal indicating data writing or reading on the second sub-device based on an interpretation result of the command signal, supply the first sub-device control signal to the second sub-device, when the device ID signal included in the main signal matches the third device ID information the first sub-device has, generate a second sub-device control signal indicating data writing or reading on the third sub-device based on the interpretation result of the command signal, and supply the second sub-device control signal to the third sub-device.

Description

CROSS REFERENCE TO RELATED APPLICATION This application claims priority from Japanese Patent Application No. 2024-194078, filed on Nov. 6, 2024. The content of this application is incorporated herein by reference in its entirety. BACKGROUND OF THE DISCLOSURE 1. Field of the Disclosure The present disclosure relates to a communication module. 2. Description of the Related Art In a semiconductor device, data transmission and reception may be performed among a plurality of devices via serial communication. In serial communication, the devices include a main device (master device) and sub-devices (slave devices) connected to the main device and, with the main device transmitting a signal to any sub-device, for example, data is written into the sub-device. The sub-device may interpret a command included in the signal from the main device and perform process in response to the command. A circuit for command interpretation has a large circuit size. Thus, when each sub-device is provided with the circuit for command interpretation, the entire circuit size also increases. Moreover, as a structure in which each sub-device is not provided with the circuit for command interpretation, U.S. Patent Application Publication No. 2017/0192918 describes a structure in which an interface circuit for interpreting a signal from the main device is provided separately from the sub-device. BRIEF SUMMARY OF THE DISCLOSURE In the structure described in U.S. Patent Application Publication No. 2017/0192918, the interface circuit is connected via a clock bus, a data bus, and an enable bus for transmitting an enable signal to a sub-device as a data transmission destination. In the structure described in U.S. Patent Application Publication No. 2017/0192918, the interface circuit selects any sub-device among the plurality of sub-devices via the enable bus to transmit data. In this case, since the enable bus is provided to each sub-device, an area for providing wiring of the enable bus is required, thereby increasing the entire circuit size. The present disclosure was made in view of these circumstances and has a possible benefit of providing a communication module the circuit size of which can be decreased. A communication module according to an aspect of the present disclosure includes: a first sub-device connected to a main device; and at least one second sub-device not connected to the main device but connected to the first sub-device via a first signal line where a clock signal is transmitted and a second signal line where a data signal is transmitted. The first sub-device receives, from the main device, a main signal including a command signal, an address signal that identifies an address of at least one register included in at least one second sub-device, and a write data signal to be recorded in a register corresponding to the address, the address signal being a signal subsequent to the command signal and the write data signal being a signal subsequent to the address signal; interprets the command signal; generates a write instruction signal based on an interpretation result of the command signal after reception of the command signal and during reception of the main signal when information based on the data signal is written in any of the at least one second sub-device; generates the data signal to be supplied based on the interpretation result of the command signal to each of the at least one second sub-device and based on the address signal and the write data signal after reception of the command signal and during reception of the main signal; and supplies the write instruction signal via the first signal line or the second signal line and the data signal via the second signal line to each of the at least one second sub-device after reception of the command signal and during reception of the main signal. Each of the at least one second sub-device determines whether the register corresponding to the address indicated by the address signal is included in the at least one second sub-device; and writes the write data signal in the register when the register is included in the at least one second sub-device and the write instruction signal is supplied from the first sub-device. A communication module according to another aspect of the present disclosure includes: a first sub-device connected to a main device to receive, from the main device, a main signal including a command signal and a device ID signal indicating a device ID for identifying a device, interpret the command signal, and have first device ID information allocated thereto; a second sub-device connected to the first sub-device via a first signal line where a clock signal is transmitted and a second signal line where a data signal is transmitted to have second device ID information allocated thereto; and a third sub-device connected to the first sub-device via a third signal line where the clock signal is transmitted and a fourth signal line where the data signal is transmit