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US-20260127132-A1 - SPI INTERFACE SYSTEM, SPI DATA WRITING METHOD, AND SPI DATA READING METHOD

US20260127132A1US 20260127132 A1US20260127132 A1US 20260127132A1US-20260127132-A1

Abstract

The present disclosure provides an SPI interface system, comprising an SPI interface module and at least one functional module; the SPI interface module is connected to an SPI master controller via an SPI_CK signal line, an SPI_MOSI signal line, and an SPI_MISO signal line; the functional module is connected to the SPI interface module. The present disclosure is suitable for application scenarios with long transmission links and is also compatible with local applications with short transmission links, providing an ideal solution for SPI transmission.

Inventors

  • Yuanlong Wang
  • Hui Wang

Assignees

  • NOREL SYSTEMS LIMITED

Dates

Publication Date
20260507
Application Date
20251229
Priority Date
20231117

Claims (16)

  1. 1 . An SPI data writing method, using an SPI interface system for data writing, and comprising: providing the SPI interface system, wherein the SPI interface system comprises an SPI interface module and at least one functional module, the SPI interface module is connected to an SPI master controller via an SPI_CK signal line, an SPI_MOSI signal line and an SPI_MISO signal line, and the functional module is connected to the SPI interface module; the SPI master controller generating a clock edge on the SPI_CK signal line and sending a write command packet to the SPI interface module via the SPI_MOSI signal line, wherein the write command packet starts with a first identifier; upon receiving the write command packet from the SPI_MOSI signal line, the SPI interface module sending the write command packet to the functional module; the functional module receiving the write command packet and executing a write command, and after completing the write command, the functional module returning a write status packet to the SPI interface module; the SPI master controller generating a clock edge on the SPI_CK signal line and reading a write feedback packet via the SPI_MISO signal line; and upon receiving the write status packet, the SPI interface module sending the write feedback packet via the SPI_MISO signal line, wherein the write feedback packet starts with a second identifier and contains status information comprised in the write status packet.
  2. 2 . The SPI data writing method according to claim 1 , wherein if the data received by the SPI interface module from the SPI_MOSI signal line reaches a length of the write command packet, the SPI interface module has received the write command packet.
  3. 3 . The SPI data writing method according to claim 1 , wherein the write command packet further comprises a write command packet checksum; and if the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the write command packet and the write command packet checksum is verified correctly, the SPI interface module has received the write command packet.
  4. 4 . The SPI data writing method according to claim 1 , wherein the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet via the SPI_MISO signal line; and if the SPI interface module does not receive the write status packet, the SPI interface module sends data that cannot be recognized as the write feedback packet to the SPI master controller via the SPI_MISO signal line.
  5. 5 . The SPI data writing method according to claim 1 , wherein the SPI interface module comprises a timeout timer; when the SPI interface module does not receive the write status packet before timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after timeout, the write feedback packet is read via the SPI_MISO signal line; and then the SPI interface module sends the write feedback packet to the SPI master controller via the SPI_MISO signal line.
  6. 6 . The SPI data writing method according to claim 1 , wherein the SPI master controller generates a clock edge on the SPI_CK signal line and sends the write command packet to the SPI interface module via the SPI_MOSI signal line; and then the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet via the SPI_MISO signal line; and after the SPI interface module sends the write feedback packet via the SPI_MISO signal line, the SPI interface module can continue to receive subsequent command packets, wherein the subsequent command packets comprise write command packets and read command packets.
  7. 7 . The SPI data writing method according to claim 1 , wherein the write feedback packet is divided into a write success feedback packet and a write failure feedback packet; the SPI master controller generates a clock edge on the SPI_CK signal line and reads the write feedback packet via the SPI_MISO signal line; if the SPI interface module receives the write status packet and the status information contained in the write status packet indicates success, the SPI interface module sends the write success feedback packet via the SPI_MISO signal line, with the write success feedback packet starting with a third identifier; and if the SPI interface module receives the write status packet and the status information contained in the write status packet indicates failure, the SPI interface module sends the write failure feedback packet via the SPI_MISO signal line, with the write failure feedback packet starting with a fourth identifier.
  8. 8 . The SPI data writing method according to claim 7 , wherein the SPI interface module comprises a timeout timer; and when the SPI interface module does not receive the write status packet before timeout, if the SPI master controller generates a clock edge on the SPI_CK signal line after timeout and reads the write feedback packet via the SPI_MISO signal line, the SPI interface module sends the write failure feedback packet to the SPI master controller via the SPI_MISO signal line.
  9. 9 . An SPI data reading method, using an SPI interface system for data reading, and comprising: providing the SPI interface system, wherein the SPI interface system comprises an SPI interface module and at least one functional module, the SPI interface module is connected to an SPI master controller via an SPI_CK signal line, an SPI_MOSI signal line and an SPI_MISO signal line, and the functional module is connected to the SPI interface module; the SPI master controller generating a clock edge on the SPI_CK signal line and sending a read command packet to the SPI interface module via the SPI_MOSI signal line, wherein the read command packet starts with a fifth identifier; after the SPI interface module receives the read command packet from the SPI_MOSI signal line, sending the read command packet to the functional module; the functional module receiving the read command packet and executing a read command, and when the functional module completes the read command, returning a read data packet to the SPI interface module; the SPI master controller generating a clock edge on the SPI_CK signal line and reading a read feedback packet via the SPI_MISO signal line; and upon receiving the read data packet, the SPI interface module sending the read feedback packet via the SPI_MISO signal line, wherein the read feedback packet starts with a sixth identifier and comprises the read data contained in the read data packet.
  10. 10 . The SPI data reading method according to claim 9 , wherein if the data received by the SPI interface module from the SPI_MOSI signal line reaches a length of the read command packet, the SPI interface module has received the read command packet.
  11. 11 . The SPI data reading method according to claim 9 , wherein the read command packet further comprises a read command packet checksum; and if the data received by the SPI interface module from the SPI_MOSI signal line reaches the length of the read command packet and the read command packet checksum is verified as correct, the SPI interface module has received the read command packet.
  12. 12 . The SPI data reading method according to claim 9 , wherein the SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet via the SPI_MISO signal line; and if the SPI interface module does not receive the read data packet, the SPI interface module sends data that cannot be recognized as the read feedback packet to the SPI master controller via the SPI_MISO signal line.
  13. 13 . The SPI data reading method according to claim 9 , wherein the SPI interface module comprises a timeout timer; and if the SPI interface module does not receive the read data packet before timeout, and after timeout, the SPI master controller generates a clock edge on the SPI_CK signal line to read the read feedback packet via the SPI_MISO signal line; and then the SPI interface module sends the read feedback packet to the SPI master controller via the SPI_MISO signal line.
  14. 14 . The SPI data reading method according to claim 9 , wherein the SPI master controller generates a clock edge on the SPI_CK signal line and sends the read command packet to the SPI interface module via the SPI_MOSI signal line; and then, the SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet via the SPI_MISO signal line; and after sending the read feedback packet via the SPI_MISO signal line, the SPI interface module can continue to receive subsequent command packets, wherein the subsequent command packets comprise read command packets and write command packets.
  15. 15 . The SPI data reading method according to claim 9 , wherein the read feedback packet is divided into a read success feedback packet and a read failure feedback packet; the SPI master controller generates a clock edge on the SPI_CK signal line and reads the read feedback packet via the SPI_MISO signal line; if the SPI interface module receives the read data packet and the status information contained in the read data packet indicates success, the SPI interface module sends the read success feedback packet via the SPI_MISO signal line, wherein the read success feedback packet starts with a seventh identifier; and if the SPI interface module receives the read data packet and the status information contained in the read data packet indicates failure, the SPI interface module sends the read failure feedback packet via the SPI_MISO signal line, wherein the read failure feedback packet starts with an eighth identifier.
  16. 16 . The SPI data reading method according to claim 15 , wherein the SPI interface module comprises a timeout timer; and if the SPI interface module does not receive the read data packet before timeout, and after timeout the SPI master controller generates a clock edge on the SPI_CK signal line to read the read feedback packet via the SPI_MISO signal line, the SPI interface module sends the read failure feedback packet to the SPI master controller via the SPI_MISO signal line.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of International Patent Application No. PCT/CN 2024/118946, filed on Sep. 14, 2024, which itself claims priority to and benefit of Chinese Patent Application No. 202311543382.8 filed on Nov. 17, 2023 in the State Intellectual Property Office of P. R. China. The disclosure of each of the above applications is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the field of communication technologies, particularly the encoding, decoding, and transmission of physical layer data, and particularly to an SPI interface system, an SPI data writing method, and an SPI data reading method. BACKGROUND SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus that uses only four pins on the chip, saving pin resources and simultaneously conserving space on the PCB layout for convenience. SPI typically consists of four signal lines: the SPI_CSN signal line, SPI_CK signal line, SPI_MOSI signal line, and SPI_MISO signal line. The SPI master controller connects to the SPI interface module via these four signal lines, with the master controller serving as the SPI master device and the interface module as the SPI slave device. The master controller drives the SPI_CSN, SPI_CK, and SPI_MOSI signal lines, while the interface module receives these signals. Conversely, the interface module drives the SPI_MISO signal line, which the master controller receives. The interface module samples the data driven by the master controller on the SPI_MOSI signal line at the rising or falling edge of the SPI_CK signal line, while the master controller samples the data driven by the interface module on the SPI_MISO signal line at the rising or falling edge of the SPI_CK signal line. In the SPI protocol, the master controller drives the SPI_CK signal line and generates clock edges on it. Both the master controller and the interface module sample data on the SPI_MISO and SPI_MOSI signal lines at these clock edges, enabling bidirectional data transfer between them. The SPI_CSN signal line serves as the select signal; data transmission occurs only when SPI_CSN is low. A single master controller can connect to multiple interface modules (i.e., one master device to multiple slave devices), sharing the SPI_CK, SPI_MOSI, and SPI_MISO signal lines among them. However, each interface module has its own dedicated SPI_CSN signal line input. When an interface module's SPI_CSN is high, it does not drive the SPI_MISO signal line (its driver output enters a Hi-Z state). An interface module drives SPI_MISO only when its SPI_CSN is low. When a master controller connects to multiple interface modules, only one module's SPI_CSN is low at any given time, preventing conflicts from multiple modules driving the SPI_MISO signal line simultaneously. When an SPI master controller is connected to only one SPI interface module, this SPI interface module can drive the SPI_MISO signal line at any time without causing conflicts. In this case, there may be no SPI_CSN signal line between the SPI master controller and the SPI interface module. That is, when an SPI master controller is connected to only one SPI interface module, the SPI master controller and the SPI interface module can be connected solely through the SPI_CK signal line, SPI_MOSI signal line, and SPI_MISO signal line. For long-distance data transmission, the process is generally based on a mode of sending a command packet and then receiving a feedback packet. The feedback packet includes status information about the execution of the command. For a read command, the feedback packet may also include read data. In the existing SPI protocol, bidirectional data transmission between the SPI master controller and the SPI interface module is achieved by sampling data on the SPI_MISO and SPI_MOSI signal lines at the rising or falling clock edges of the SPI_CK signal line. However, this data transmission can be considered a form of data stream transmission and is not suitable for long-distance data transmission. Currently, there is a lack of a solution for long-distance data transmission via SPI interface signals based on the existing SPI protocol. SUMMARY To address the issue in the prior art where the SPI protocol cannot support long-distance transmission, an object of the present disclosure is to provide an SPI interface system. The SPI interface system includes an SPI interface module and at least one functional module. The SPI interface module is connected to the SPI master controller via the SPI_CK signal line, SPI_MOSI signal line, and SPI_MISO signal line, and the functional module is connected to the SPI interface module. Another object of the present disclosure is to provide an SPI data writing method, which uses an SPI interface system for data writing and comprises: the SPI master controller generating a clock edge on the SPI_CK signal line and