US-20260127135-A1 - SIGNAL PROCESSING AND TRANSMISSION IN ELECTRONIC CIRCUITS

US20260127135A1US 20260127135 A1US20260127135 A1US 20260127135A1US-20260127135-A1

Abstract

An integrated circuit (IC) chip receives an input signal on a bus connecting a number of IC chips in series. The IC chip is one of the number of IC chips. The IC chip performs a combining operation and an inverting operation on a signal produced by the IC chip and the input signal to generate an output signal. The IC chip sends the output signal to a next chip of the number of IC chips on the bus.

Inventors

David Carlson
Tao Xu

Assignees

Auradine, Inc.

Dates

Publication Date: 20260507
Application Date: 20260102

Claims (20)

1 - 30 . (canceled)
31 . A method for signal processing, the method comprising: receiving, by an integrated circuit (IC) chip of a plurality of IC chips, a first input signal on a first bus connecting the plurality of IC chips in series; selectively performing, by the IC chip based on a position of the IC chip within the plurality of IC chips along the first bus, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on a signal produced by the IC chip and the first input signal to generate a first output signal; and sending, by the IC chip, the first output signal to a next chip of the plurality of IC chips on the first bus.
32 . The method of claim 31 , wherein the first input signal is received from a previous chip of the plurality of IC chips connected in series on the first bus, and wherein the first input signal comprises a result of a computation operation performed by the previous chip, and wherein the signal produced by the IC chip comprises a result of a computation operation performed by the IC chip.
33 . The method of claim 31 , wherein the plurality of IC chips are sequentially ordered by a first set of integer indices in a first transmission direction of signals on the first bus, and wherein each IC chip is operable to selectively perform a combining operation followed by an inverting operation, or an inverting operation followed by a combining operation depending on whether an integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus.
34 . The method of claim 33 , wherein selectively performing, by the IC chip based on a position of the IC chip within the plurality of IC chips along the first bus, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on a signal produced by the IC chip and the first input signal to generate a first output signal comprises: based at least on whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus, selectively performing, by the IC chip, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on the signal produced by the IC chip and the first input signal to generate the first output signal.
35 . The method of claim 34 , comprising: determining, by the IC chip, whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus, wherein determining the whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus comprises: determining that the first bus is in an idle state; and in response to determining that the first bus is in the idle state, determining that the integer index of the IC chip is even in the first transmission direction of signals on the first bus when an input signal to the IC chip indicates a first logic state; or in response to determining that the first bus is in the idle state, determining that the integer index of the IC chip is odd in the first transmission direction of signals on the first bus when an input signal to the IC chip indicates a second logic state, wherein the first logic state is one of a logic high state or a logic low state, and the second logic state is the other one of the logic high state or the logic low state.
36 . The method of claim 31 , wherein the plurality of IC chips are sequentially ordered by a second set of integer indices in a second transmission direction of signals on a second bus, the method further comprising: receiving, by the IC chip, a second input signal on the second bus connecting the plurality of IC chips in series; performing, by the IC chip, an inverting operation on the second input signal to generate a second output signal; sending, by the IC chip, the second output signal to the next chip on the second bus; and determining, by the IC chip, whether an integer index of the IC chip is even or odd in the second transmission direction of signals on the second bus, wherein the first bus is a response bus, and the second bus is a command bus.
37 . The method of claim 36 , wherein determining whether the integer index of the IC chip is even or odd in the second transmission direction of signals on the second bus comprises: determining that the second bus is in an idle state; and in response to determining that the second bus is in the idle state, determining that the integer index of the IC chip is one of (i) even in the second transmission direction of signals on the second bus when an input signal to the IC chip indicates a first logic state, or (ii) odd in the second transmission direction of signals on the second bus when an input signal to the IC chip indicates a second logic state.
38 . The method of claim 37 , further comprising one of: in response to determining that the integer index of the IC chip is even in the second transmission direction of signals on the second bus, sending the second input signal to a controller circuit of the IC chip; or in response to determining that the integer index of the IC chip is odd in the second transmission direction of signals on the second bus, sending the second output signal to the controller circuit of the IC chip, wherein the controller circuit is configured to provide the signal produced by the IC chip for the combining operation.
39 . An electronic circuit comprising: a plurality of integrated circuit (IC) chips that are series connected using a plurality of buses, wherein an IC chip of the plurality of IC chips comprises: a plurality of input terminals on a plurality of buses connected to the IC chip, wherein the plurality of input terminals are coupled to output terminals of an upstream neighboring chip of a plurality of chips that is series connected to the IC chip using the plurality of buses; a plurality of output terminals on the plurality of buses, wherein the plurality of output terminals are coupled to input terminals of a downstream neighboring chip of the plurality of chips, wherein the plurality of chips comprises the IC chip, the upstream neighboring chip and the downstream neighboring chip; wherein the plurality of IC chips are sequentially ordered by a first set of integer indices in a first transmission direction of signals on a first bus of the plurality of buses, and wherein each IC chip is operable to selectively perform a combining operation followed by an inverting operation, or an inverting operation followed by a combining operation depending on whether an integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus; and a first circuit for processing signals on the first bus, the first circuit configured to: receive a first input signal on a first bus connecting the plurality of IC chips in series; selectively perform, based on a position of the IC chip within the plurality of IC chips along the first bus, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on a signal produced by the IC chip and the first input signal to generate a first output signal; and send the first output signal to a next chip of the plurality of IC chips on the first bus.
40 . The electronic circuit of claim 39 , wherein the first input signal is received from a previous chip of the plurality of IC chips connected in series on the first bus, and wherein the first input signal comprises a result of a computation operation performed by the previous chip, and wherein the signal produced by the IC chip comprises a result of a computation operation performed by the IC chip.
41 . The electronic circuit of claim 39 , wherein selectively performing, based on a position of the IC chip within the plurality of IC chips along the first bus, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on a signal produced by the IC chip and the first input signal to generate a first output signal comprises: based at least on whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus, selectively performing, by the IC chip, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on the signal produced by the IC chip and the first input signal to generate the first output signal.
42 . The electronic circuit of claim 41 , wherein the first circuit is further configured to: determine whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus, wherein determining the whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus comprises: determine that the first bus is in an idle state; and in response to determining that the first bus is in the idle state, determine that the integer index of the IC chip is even in the first transmission direction of signals on the first bus when an input signal to the IC chip indicates a first logic state; or in response to determining that the first bus is in the idle state, determine that the integer index of the IC chip is odd in the first transmission direction of signals on the first bus when an input signal to the IC chip indicates a second logic state, wherein the first logic state is one of a logic high state or a logic low state, and the second logic state is the other one of the logic high state or the logic low state.
43 . The electronic circuit of claim 39 , wherein the plurality of IC chips are sequentially ordered by a second set of integer indices in a second transmission direction of signals on a second bus, the first circuit is further configured to: receive a second input signal on the second bus connecting the plurality of IC chips in series; perform an inverting operation on the second input signal to generate a second output signal; send the second output signal to the next chip on the second bus; and determine whether an integer index of the IC chip is even or odd in the second transmission direction of signals on the second bus, wherein the first bus is a response bus, and the second bus is a command bus.
44 . The electronic circuit of claim 43 , wherein determining whether the integer index of the IC chip is even or odd in the second transmission direction of signals on the second bus comprises: determine that the second bus is in an idle state; and in response to determining that the second bus is in the idle state, determine that the integer index of the IC chip is one of (i) even in the second transmission direction of signals on the second bus when an input signal to the IC chip indicates a first logic state, or (ii) odd in the second transmission direction of signals on the second bus when an input signal to the IC chip indicates a second logic state.
45 . The electronic circuit of claim 44 , wherein the IC chip further comprises a controller circuit, and the first circuit is further configured to: in response to determining that the integer index of the IC chip is even in the second transmission direction of signals on the second bus, send the second input signal to a controller circuit of the IC chip; or in response to determining that the integer index of the IC chip is odd in the second transmission direction of signals on the second bus, send the second output signal to the controller circuit of the IC chip, wherein the controller circuit is configured to provide the signal produced by the IC chip for the combining operation.
46 . An integrated circuit (IC) chip, comprising: a plurality of input terminals on a plurality of buses connected to the IC chip, wherein the plurality of input terminals are coupled to output terminals of an upstream neighboring chip of a plurality of chips that is series connected to the IC chip using the plurality of buses; a plurality of output terminals on the plurality of buses, wherein the plurality of output terminals are coupled to input terminals of a downstream neighboring chip of the plurality of chips, wherein the plurality of chips comprises the IC chip, the upstream neighboring chip and the downstream neighboring chip; wherein the plurality of IC chips are sequentially ordered by a first set of integer indices in a first transmission direction of signals on a first bus of the plurality of buses, and wherein each IC chip is operable to selectively perform a combining operation followed by an inverting operation, or an inverting operation followed by a combining operation depending on whether an integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus; and a first circuit for processing signals on the first bus, the first circuit configured to: receive a first input signal on a first bus connecting the plurality of IC chips in series; selectively perform, based on a position of the IC chip within the plurality of IC chips along the first bus, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on a signal produced by the IC chip and the first input signal to generate a first output signal; and send the first output signal to a next chip of the plurality of IC chips on the first bus.
47 . The IC chip of claim 46 , wherein the first input signal is received from a previous chip of the plurality of IC chips connected in series on the first bus, and wherein the first input signal comprises a result of a computation operation performed by the previous chip, and wherein the signal produced by the IC chip comprises a result of a computation operation performed by the IC chip.
48 . The IC chip of claim 46 , wherein selectively performing, based on a position of the IC chip within the plurality of IC chips along the first bus, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on a signal produced by the IC chip and the first input signal to generate a first output signal comprises: based at least on whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus, selectively performing, by the IC chip, a combining operation followed by an inverting operation, or an inverting operation followed by a combing operation, on the signal produced by the IC chip and the first input signal to generate the first output signal.
49 . The IC chip of claim 48 , wherein the first circuit is further configured to: determine whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus, wherein determining the whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus comprises: determine that the first bus is in an idle state; and in response to determining that the first bus is in the idle state, determine that the integer index of the IC chip is even in the first transmission direction of signals on the first bus when an input signal to the IC chip indicates a first logic state; or in response to determining that the first bus is in the idle state, determine that the integer index of the IC chip is odd in the first transmission direction of signals on the first bus when an input signal to the IC chip indicates a second logic state, wherein the first logic state is one of a logic high state or a logic low state, and the second logic state is the other one of the logic high state or the logic low state.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application and claims priority under 35 U.S.C. § 120 to U.S. patent application Ser. No. 18/217,185, filed on Jun. 30, 2023. The foregoing application is incorporated herein by reference in its entirety. TECHNICAL FIELD The following disclosure generally relates to signal processing and transmission, and more specifically, to methods, integrated circuit (IC) chips, and electronic circuits related to processing and transmitting signals with reduced latency. BACKGROUND An electronic circuit can include multiple IC chips arranged in a particular topology, e.g., in series, in parallel, or a combination of both. Each of the IC chips in the electronic circuit can communicate with its neighboring chips. SUMMARY The present disclosure describes methods, integrated circuit (IC) chips, and electronic circuits to process and transmit signals with reduced latency. An electronic circuit includes a number of IC chips connected in series using multiple buses. The IC chips are connected such that input terminals of one IC chip are connected to output terminals of an upstream neighboring IC chip, and output terminals of the IC chip are connected to input terminals of a downstream neighboring IC chip. Each IC chip can receive an input signal from its upstream neighboring IC chip, combine its own signal with the input signal to generate a combined signal, and transmit the combined signal as an output signal to its downstream neighboring IC chip. By using the above combine-and-forward method, the output signal can be promptly transmitted without undergoing synchronization or retiming processes. By eliminating store-and-forward mechanism for data, the circuit minimizes delays typically incurred during those processes. The combining and forwarding of the signals enable swift transmission without latency-inducing operations. Each IC chip includes components to invert communication signals at each chip. This deliberate inversion serves as a beneficial measure to prevent the accumulation of a specific class of noise. By inverting the signal at each chip, the noise that may have been introduced in previous stages of the circuit is counteracted, thus maintaining signal integrity. Each IC chip possesses the ability to self-discover its position within the electronic circuit, allowing it to determine whether it has an odd or even configuration in an ordered arrangement of the number of IC chips in the electronic circuit. This self-discovery enables the IC chip to handle the inversion of the communication signals internally, ensuring that the overall electronic circuit functions as intended. In a general aspect, an IC chip performs a method that comprises: receiving a first input signal on a first bus connecting a plurality of IC chips in series; performing a combining operation and an inverting operation on a signal produced by the IC chip and the first input signal to generate a first output signal; and sending the first output signal to a next chip of the plurality of IC chips on the first bus. Particular implementations may include one or more of the following features. In some implementations, the first input signal is received from a previous chip of the plurality of IC chips connected in series on the first bus. In some implementations, the first input signal comprises a result of a computation operation performed by the previous chip, and wherein the signal produced by the IC chip comprises a result of a computation operation performed by the IC chip. In some implementations, the first output signal sent by the IC chip corresponds to an input signal for the next chip on the first bus. In such implementations, the method performed by the IC chip further comprises: performing a combining operation and an inverting operation on a signal produced by of the next chip and the first output signal to generate an output signal of the next chip. In some implementations, the method performed by the IC chip further comprises: determining an evenness or oddness of the IC chip with respect to a first signal transmission direction on the first bus, wherein the evenness or oddness of the IC chip represents an even or odd numbering of the IC chip in a positioning arrangement of the plurality of IC chips connected in series. In such implementations, determining the evenness or oddness of the IC chip with respect to the first signal transmission direction on the first bus comprises: determining that the first bus is in an idle state; and in response to determining that the first bus is in the idle state, determining that the IC chip is an even chip with respect to the first signal transmission direction when an input signal to the IC chip indicates a first logic state; or in response to determining that the first bus is in the idle state, determining that the IC chip is an odd chip with respect to the first signal transmission direction when an input signal to the IC chip i