US-20260127343-A1 - INTERFACING METHOD FOR RTL SIMULATION OF INTEGRATED CIRCUITS AND SYSTEM PERFORMING SAME

US20260127343A1US 20260127343 A1US20260127343 A1US 20260127343A1US-20260127343-A1

Abstract

The present disclosure relates to an interfacing method for RTL simulation of an integrated circuit and a system performing the same. The method comprises: obtaining a clock gating time during which a clock supplied to the integrated circuit is gated; obtaining a data holding time during which the clock is not gated but input data do not switch; and providing a metric corresponding to a ratio, within a unit time, occupied by the clock gating time and the data holding time.

Inventors

In Hak HAN
Ju Hyeong PARK

Assignees

BAUM DESIGN SYSTEMS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250818
Priority Date: 20241106

Claims (10)

1 . An interfacing method for Register Transfer Level (RTL) design simulation of an integrated circuit performed by a processor, the method comprising: obtaining a clock gating time during which a clock is gated with respect to the integrated circuit; obtaining a data holding time during which the clock is not gated and input data does not switch; and interfacing a first metric corresponding to a ratio of the clock gating time and the data holding time to a unit time to a user device.
2 . The method of claim 1 , wherein the first metric is determined according to an equation: M = t g + t c t s wherein M refers to the first metric, t g refers to the clock gating time, t c refers to the data holding time, and t s refers to the unit time.
3 . The method of claim 1 , further comprising: calculating a second metric corresponding to a clock gating ratio; receiving a scenario time; and interfacing a graph of the second metric per unit time, for the scenario time.
4 . The method of claim 3 , further comprising: receiving a target metric value; and indicating, using an indicator, a unit time during which the second metric does not satisfy the target metric value.
5 . The method of claim 4 , further comprising: receiving a selection instruction for the indicator; and displaying an expanded graph in which a time axis of a unit time corresponding to the indicator is extended based on the selection instruction, wherein the indicator highlights corresponding time interval with a predetermined color and the expanded graph is also highlighted with the predetermined color.
6 . The method of claim 3 , wherein the interfacing the graph of the second metric comprises: calculating the second metric per unit time for a first RTL circuit; providing a first graph depicting the second metric per unit time for the first RTL circuit along a time flow of the clock; calculating the second metric per unit time for a second RTL circuit; providing a second graph depicting the second metric per unit time for the second RTL circuit along a time flow of the clock; and indicating unit times that are not identical between the first graph and the second graph.
7 . The method of claim 6 , wherein the indicating unit times that are not identical between the first graph and the second graph comprises: highlighting, with a first color, unit times in which the second metric per unit time for the first RTL circuit is higher than the second metric per unit time for the second RTL circuit; and highlighting, with a second color, unit times in which the second metric per unit time for the first RTL circuit is lower than the second metric per unit time for the second RTL circuit.
8 . The method of claim 3 , wherein the interfacing the graph of the second metric comprises: calculating the second metric per unit time for a first clock domain in the RTL circuit to which a first clock is applied; calculating the second metric per unit time for a second clock domain in the RTL circuit to which a second clock is applied; and indicating the second metric for each of the first clock domain and the second clock domain.
9 . The method of claim 8 , wherein the interfacing the graph of the second metric further comprises: calculating an integrated metric by performing a weighted sum of the second metric per unit time for the first clock domain and the second metric per unit time for the second clock domain, wherein the weight of the weighted sum is determined based on a frequency ratio of the first clock and the second clock, or a ratio of clock cycle counts into which the first clock and the second clock are input.
10 . The method of claim 9 , wherein the integrated metric is calculated based on the equation below: M tot = M A · N A · f A + M B · N B · f B N A · f A + N B · f B wherein M tot refers to the integrated metric, M A refers to the second metric per unit time for the first clock domain, N A refers to the number of flip-flops driven by the first clock, f A refers to the frequency of the first clock, M B refers to the second metric per unit time for the second clock domain, N B refers to the number of flip-flops driven by the second clock, and f B refers to the frequency of the second clock.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0155823, filed on Nov. 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND Technical Field The present disclosure relates to a method for interfacing Register Transfer Level (RTL) simulation of an integrated circuit, and more particularly, to a method for interfacing various metrics that facilitate RTL simulation and to a system that performs the same. Background Art An integrated circuit (IC) is an electronic device in which diverse functions such as computation and storage are integrated on a single semiconductor chip. As society becomes increasingly sophisticated, various types of mobile devices are being developed. By incorporating integrated circuit devices, mobile devices pursue miniaturization and weight reduction. A drawback of mobile devices is that they rely on limited power sources such as batteries. To extend the operating lifetime of mobile devices, research is being conducted on both increasing battery capacity and low-power design of integrated circuit devices. Predicting the power consumption of integrated circuit devices is a prerequisite to achieving low-power design. For this purpose, the RTL simulation method is utilized. RTL design is a descriptive technique that, when designing an integrated circuit, specifies the data flow and the logical operations that process the data. Such RTL design utilizes a clock gating technique. Clock gating is an important technique for reducing power consumption in digital circuits. When a portion of the circuit is not in use, the clock signal to that portion is disabled, thereby reducing dynamic power consumption. If a part of the circuit is unnecessary for a certain period, clock gating can block the clock signal to that part, thereby preventing unnecessary power consumption. Various indices such as Clock Gating Efficiency (CGE) and Operational Clock Gating Ratio (OCGR) have been developed to utilize the clock gating technique efficiently. However, these indices fail to reflect whether data switching occurs, and therefore are insufficient as representative indicators for efficient clock gating. SUMMARY Technical Problem A technical objective of the present disclosure is to provide a method for interfacing a metric that can simultaneously reflect both clock gating status and data switching status, and to provide a system performing the same. Another technical objective of the present disclosure is to provide various interfacing methods that can efficiently present a metric to a user. Technical Solution An interfacing method for Register Transfer Level (RTL) design simulation of an integrated circuit according to the technical idea of the present disclosure may include: obtaining a clock gating time during which a clock is gated with respect to the integrated circuit; obtaining a data holding time during which the clock is not gated and input data does not switch; and providing a metric corresponding to a ratio of the clock gating time and the data holding time to a unit time In one embodiment, the metric may be determined according to the equation below: M=tg+tcts Wherein tg refers to the clock gating time, tc refers to the data holding time, and ts refers to the unit time. In one embodiment, the method may further include: calculating a second metric corresponding to a clock gating ratio; receiving a scenario time; and, for the scenario time, interfacing a graph of the second metric per unit time. In one embodiment, the method may further include: receiving a target metric value; and indicating, using an indicator, a unit time during which the second metric does not satisfy the target metric value. In one embodiment, the method may further include: receiving a selection instruction for the indicator; and displaying an expanded graph in which a time axis of a unit time corresponding to the indicator is extended based on the selection instruction, wherein the indicator highlights corresponding time interval with a predetermined color and the expanded graph is also highlighted with the predetermined color. In one embodiment, interfacing the graph of the second metric may include: calculating the second metric per unit time for a first RTL circuit; providing a first graph depicting the second metric per unit time for the first RTL circuit along a time flow of the clock; calculating the second metric per unit time for a second RTL circuit; providing a second graph depicting the second metric per unit time for the second RTL circuit along a time flow of the clock; and indicating unit times that are not identical between the first graph and the second graph. In one embodiment, indicating the unit times that are not identical between the first graph and the second graph may include: highlighting, with a first color, unit times in which the second metric per unit time for the first RTL cir