US-20260127346-A1 - SYSTEMS AND METHODS FOR CALIBRATING SEMICONDUCTOR PROCESS EMULATION MODELS

US20260127346A1US 20260127346 A1US20260127346 A1US 20260127346A1US-20260127346-A1

Abstract

Systems and methods for automated calibration of semiconductor process emulation models. The method includes accessing process data for a foundry process node and process node revision, wherein the process data includes a plurality of process parameters. The processor-implemented method receives target feature(s) and generates predicted output which are cross-sectional images of the target feature(s), based on the value of the semiconductor process emulation model parameters. The method compares the predicted output to actual measurements of the target feature(s) obtained from characterization data. The method automatically calibrates the process emulation model by varying the values of model parameters (the input to the semiconductor process models) and generating respective predicted output. The method evaluates the predicted output based on a supplied error criteria and error value. The method iterates until the determined error is less than or equal to a supplied error value.

Inventors

Santosh Tripathi
Timothy Crimmins

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260507
Application Date: 20241107

Claims (20)

1 . A method comprising: accessing a semiconductor process emulation model having a plurality of model parameters; accessing process data for a foundry process node and process node revision; receiving an error criteria and an error value; generating, for at least one model parameter of the plurality of model parameters, a respective one or more alternate values; and wherein the respective one or more alternate values, when processed in the semiconductor process emulation model, generate a final predicted output; wherein the final predicted output has a target feature with a final measurement; wherein the final measurement, when evaluated with the error criteria, varies from a respective actual measurement by less than or equal to the error value.
2 . The method of claim 1 , wherein generating, for the at least one model parameter of the plurality of model parameters, the respective one or more alternate values, comprises: for a first model parameter of the plurality of model parameters: predicting a first intermediate predicted output that is based on the process data with the first model parameter equal to a first value; wherein the first intermediate predicted output has the target feature with a first measurement; wherein the first measurement, when evaluated with the error criteria, varies from the respective actual measurement by more than the error value; and predicting a second intermediate predicted output that is based on the process data with the first model parameter equal to a second value; wherein the second intermediate predicted output has the target feature with a second measurement; wherein the second measurement, when evaluated with the error criteria, varies from the respective actual measurement by more than the error value; and generating a third value for the first model parameter when both the first predicted measurement and the second predicted measurement vary from the respective actual measurement by more than the error value.
3 . The method of claim 2 , further comprising: calculating a gradient between the first measurement and the second measurement; wherein generating the third value for the first model parameter parameters is based on the gradient.
4 . The method of claim 2 , further comprising: generating, for individual model parameters of a remainder of the plurality of model parameters, a respective plurality of alternate values.
5 . The method of claim 4 , wherein generating, for the plurality of model parameters, the respective one or more alternate values further comprises: applying one or more methods from among enumerative search, parameter continuation, trajectory search, relaxation methods, branch-and-bound, random search, Bayesian search, adaptive stochastic search, evolutionary search, simulated annealing, and tabu search.
6 . The method of claim 2 , further comprising: generating a third intermediate predicted output based on the process data with the first model parameter equal to the third value.
7 . The method of claim 1 , further comprising: receiving a cost function; and calculating the final measurement using the cost function.
8 . The method of claim 7 , further comprising: determining a curvature of a profile of the target feature in the final predicted output; and determining the final measurement includes weighting the cost function based on the curvature of the profile.
9 . The method of claim 7 , further comprising: pixelating the final predicted output to create a pixelated predicted image; pixelating a source of the respective actual measurement to create a pixelated actual image; wherein the cost function is a material-sin-product (MSP), calculating the MSP as a count of pixels; determining a first material near the target feature in the pixelated predicted image and a second material near the target feature in the pixelated actual image; and the final measurement is a function of a number of pixels for which the first material and the second material are not equal.
10 . The method of claim 9 , further comprising: determining a curvature of the second material around the target feature; and weighting individual pixels based on the curvature of the second material.
11 . One or more computer-readable storage media storing computer-executable instructions which when executed by a processor cause the processor to perform a method, the method comprising: accessing process data for a foundry process node; accessing a semiconductor process emulation model to operate on the process data, the semiconductor process emulation model having a plurality of model parameters; generating one or more alternate values of model parameters for a respective one or more model parameters of the plurality of model parameters; and wherein, responsive to a vector comprising the one or more alternate values of model parameters, the semiconductor process emulation model generates a final predicted output; wherein the final predicted output has a target feature with a final measurement that varies from a respective actual measurement by less than or equal to an error value.
12 . The one or more computer-readable storage media of claim 11 , wherein the method further comprises: accessing an error criteria; and wherein the final measurement, when evaluated with the error criteria, varies from the respective actual measurement by less than or equal to the error value.
13 . The one or more computer-readable storage media of claim 12 , wherein the method further comprises: for a first model parameter of the plurality of model parameters: predicting a first intermediate predicted output that is based on the process data with the first model parameter equal to a first value; wherein the first intermediate predicted output has the target feature with a first measurement; wherein the first measurement, when evaluated with the error criteria, varies from the respective actual measurement by more than the error value; and predicting a second intermediate predicted output that is based on the process data with the first model parameter equal to a second value; wherein the second intermediate predicted output has the target feature with a second measurement; wherein the second measurement, when evaluated with the error criteria, varies from the respective actual measurement by more than the error value; and generating a third value for the first model parameter when both the first predicted measurement and the second predicted measurement vary from the respective actual measurement by more than the error value.
14 . The one or more computer-readable storage media of claim 13 , wherein the method further comprises: calculating a gradient between the first measurement and the second measurement; wherein generating the third value for the first model parameter is based on the gradient.
15 . The one or more computer-readable storage media of claim 11 , wherein generating the one or more alternate values of the model parameters for the respective one or more model parameters of the plurality of model parameters further comprises: applying one or more methods from among enumerative search, parameter continuation, trajectory search, relaxation methods, branch-and-bound, random search, Bayesian search, adaptive stochastic search, evolutionary search, simulated annealing, and tabu search.
16 . The one or more computer-readable storage media of claim 12 , wherein the method further comprises: receiving a cost function; and determining the final measurement using the cost function.
17 . The one or more computer-readable storage media of claim 16 , wherein the method further comprises: determining a curvature of a profile of the target feature in the final predicted output; wherein determining the final measurement using the cost function is weighted based on the curvature of the profile.
18 . The one or more computer-readable storage media of claim 17 , wherein the method further comprises: pixelating the final predicted output to create a pixelated predicted image; pixelating a source of the respective actual measurement to create a pixelated actual image; wherein the cost function is a material-sin-product (MSP), calculating the MSP as a count of pixels; determining a first material near the target feature in the pixelated predicted image and a second material near the target feature in the pixelated actual image; and the final measurement is a function of a number of pixels for which the first material and the second material are not equal.
19 . An apparatus, comprising: circuitry to: access process data for a foundry process node; receive a target feature; access characterization data for the foundry process node; access a semiconductor process emulation model to operate on the process data, the semiconductor process emulation model having a plurality of model parameters; and generate a vector comprising one or more alternate values for the plurality of model parameters; wherein, responsive to the vector comprising the one or more alternate values, the semiconductor process emulation model generates a final predicted output; wherein the final predicted output has a target feature with a final measurement that varies from a respective actual measurement by less than or equal to an error value.
20 . The apparatus of claim 19 , wherein the circuitry is further to: access an error criteria; and wherein the final measurement, when evaluated with the error criteria, varies from the respective actual measurement by less than or equal to the error value.

Description

BACKGROUND To enable a semiconductor manufacturing process to have a high yield of high-performance devices, the three-dimensional semiconductor device structure and structural variability achieved by the semiconductor manufacturing process must be well-characterized and understood. Semiconductor process emulation models are often at least a part of this characterization process. Continued improvements to these semiconductor process emulation models are desirable. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram depicting an example environment in which embodiments may operate. FIG. 2 provides a non-limiting example of architectural block diagram of one or more application modules that may be operating in the system for calibrating semiconductor process emulation models, in accordance with various embodiments. FIG. 3 illustrates an exemplary method for calibrating semiconductor process emulation models, in accordance with various embodiments. FIG. 4 is a top view of a wafer and dies that may have been fabricated and characterized, in accordance with any of the embodiments disclosed herein. FIG. 5 is a simplified cross-sectional side view showing an implementation of an integrated circuit on a die that may include various features that may be target features, in accordance with any of the embodiments disclosed herein. FIG. 6 is a cross-sectional side view of a microelectronic assembly that may be constructed pursuant to any of the embodiments disclosed herein. FIG. 7 illustrates an exemplary compute node, on which embodiments may operate. DETAILED DESCRIPTION To enable a semiconductor manufacturing process to have a high yield of high-performance devices, the three-dimensional semiconductor device structure and structural variability achieved by the semiconductor manufacturing process must be well-characterized and understood. Properly characterizing a library for a target foundry process and version/release is technically challenging. Semiconductor process emulation is often at least a part of this characterization process. Target features are referred to herein. Target features may be part of a standard cell. As is understood by those with skill in the art, a standard cell is a function in digital logic; it can be a simple function, like an inverter, or a more complex gate or sequential element. A plurality of standard cells, embodied as intellectual property (IP) cores, which are reusable units of logic and/or layout for standard cells, is sometimes referred to as a library. The libraries include geometries and margins, for example, the length, width, and thickness of a metal trace or gate, and its margin, such as +/−20%. Semiconductor process emulation takes fabrication process information and parameters and predicts wafer output (and how those standard cells and target features appear) based thereon. Available standard characterization methods generally rely on running silicon experiments and then collecting transmission electron microscopy (TEM), E-Test, optical critical dimension (OCD), and other data. After collecting the data, the data is stored and models used for emulating the semiconductor process are manually revised. Additionally, the fabrication process/version can have inherent issues that are not discovered until the product is fabricated and tested, such as, during failure analysis. A product may not be functional or may have a low yield using a given library because of a standard cell defect that occurs because of a manufacturing fabrication issue rather than due to a faulty design. In combination, available methods for calibrating semiconductor process emulation models are technically challenging and have a turn-around time of weeks to months, which is a disadvantage. Embodiments provide a technical solution to these technical problems and other related enhancements, in the form of systems and methods for calibrating semiconductor process emulation models. Embodiments automatically calibrate semiconductor process emulation models so that the predictions from ‘Semiconductor Process Emulation’ matches with what is physically observed when wafers are physically processed using that semiconductor process for wafer fabrication. Some embodiments implement machine learning (ML) or artificial intelligence (AI) to perform some of the processing described herein. Provided embodiments introduce a predictive self-calibrating method to reduce this turnaround time, increasing process yield and performance ramps. Aspects of this disclosure can be detected with a visual inspection of release notes from third-party suppliers of libraries, the release notes would accompany a process node and/or process node revision release. If the release notes reference or supply cross sectional device images that are not direct from physical sectioning, this can indicate the presence of the herein disclosed embodiments. A more detailed description of the aspects of the present disclosure follows a terminology