US-20260127347-A1 - INTEGRATED CIRCUIT DESIGN USING NEURAL NETWORKS

Abstract

Apparatuses, systems, and methods cause one or more neural networks to generate one or more representations of one or more integrated circuits. In at least one embodiment, a processor comprises one or more circuits to use one or more neural networks to generate one or more representations of one or more integrated circuits to perform one or more instructions, wherein the one or more representations are based, at least in part, on one or more different instruction operands and one or more representations resulting from the one or more different instruction operands.

Inventors

• Chong Yu

Assignees

• NVIDIA CORPORATION

Dates

Publication Date

20260507

Application Date

20241118

Priority Date

20241101

Claims (20)

1. 1 . A processor comprising: one or more circuits to use one or more neural networks to generate one or more representations of one or more integrated circuits to perform one or more instructions, wherein the one or more representations are based, at least in part, on one or more different instruction operands and one or more representations resulting from the one or more different instruction operands.
2. 2 . The processor of claim 1 , wherein the one or more different instruction operands correspond to one or more different tests of the one or more instructions.
3. 3 . The processor of claim 1 , wherein one or more different tests of the one or more instructions are generated based, at least in part, on performing one or more different tests.
4. 4 . The processor of claim 1 , wherein the one or more circuits are to iteratively generate the one or more representations based, at least in part, on one or more second tests of the one or more instructions generated based, at least in part, on one or more first tests of the one or more instructions.
5. 5 . The processor of claim 1 , wherein the one or more circuits are to fine-tune the one or more neural networks based, at least in part, on one or more different tests corresponding to the one or more different instruction operands.
6. 6 . The processor of claim 1 , wherein the one or more circuits are to generate the one or more representations based, at least in part, on input comprising one or more different tests corresponding to the one or more different instruction operands.
7. 7 . The processor of claim 1 , wherein the one or more circuits are to generate one or more tests of the one or more representations based, at least in part, on one or more definitions of an instruction set to be implemented by the one or more representations of the one or more integrated circuits.
8. 8 . A method, comprising: using one or more neural networks to generate one or more representations of one or more integrated circuits to perform one or more instructions, wherein the one or more representations are based, at least in part, on one or more different instruction operands and one or more representations resulting from the one or more different instruction operands.
9. 9 . The method of claim 8 , wherein the one or more different instruction operands correspond to one or more different tests to test the one or more representations.
10. 10 . The method of claim 8 , wherein one or more different tests of the one or more instructions performed by the one or more representations are generated based, at least in part, on performing one or more different tests.
11. 11 . The method of claim 8 , further comprising: iteratively generating the one or more representations based, at least in part, on one or more second tests of the one or more instructions generated based, at least in part, on one or more first tests of the one or more instructions.
12. 12 . The method of claim 8 , further comprising: fine-tuning the one or more neural networks based, at least in part, on one or more different tests corresponding to the one or more different instruction operands.
13. 13 . The method of claim 8 , wherein the one or more representations are generated based, at least in part, on input comprising one or more different tests corresponding to the one or more different instruction operands.
14. 14 . The method of claim 8 , further comprising: generating one or more tests of the one or more representations based, at least in part, on one or more definitions of an instruction set to be implemented by the one or more representations of the one or more integrated circuits.
15. 15 . A system, comprising: one or more processors to use one or more neural networks to generate one or more representations of one or more integrated circuits to perform one or more instructions, wherein the one or more representations are based, at least in part, on one or more different instruction operands and one or more representations resulting from the one or more different instruction operands.
16. 16 . The system of claim 15 , wherein the one or more different instruction operands are used to generate one or more different tests to test the one or more representations.
17. 17 . The system of claim 15 , wherein the one or more representations are tested to test one or more performance features of the one or more instructions.
18. 18 . The system of claim 15 , wherein the one or more neural networks comprise a large language model (LLM) used to identify the one or more instructions from an instruction set architecture (ISA).
19. 19 . The system of claim 15 , wherein the one or more different instruction operands are correlated to unsatisfactory outputs of one or more tests of the one or more instructions.
20. 20 . The system of claim 15 , wherein unsatisfactory outputs of the one or more representations are used to update the one or more neural networks.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Patent Application No. PCT/CN2024/129355, filed on Nov. 1, 2024, entitled “INTEGRATED CIRCUIT DESIGN USING NEURAL NETWORKS,” the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD Apparatuses, systems, and methods to cause one or more neural networks to generate one or more integrated circuit representations. In at least one embodiment, a processor comprises one or more circuits to use one or more neural networks to generate one or more representations of one or more integrated circuits to perform one or more instructions, wherein the one or more representations are based, at least in part, on one or more different instruction operands and one or more representations resulting from the one or more different instruction operands. BACKGROUND Processes for generating designs for integrated circuits uses considerable time and computing resources. These processes can be improved. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 illustrates a system to perform test case generation for integrated circuit chip design using a neural network, according to at least one embodiment; FIG. 2 illustrates a workflow to perform automated design of a circuit chip, according to at least one embodiment; FIG. 3 illustrates an automated generation of test cases for circuit chip design, according to at least one embodiment; FIG. 4 illustrates a process to train and use a neural network to generate code for automated integrated circuit representation design, according to at least one embodiment; FIG. 5 illustrates a flowchart of a method of training a neural network to be used with an automated integrated circuit representation design process, according to at least one embodiment; FIG. 6 illustrates a first portion 600 of an automated integrated circuit representation design process, according to at least one embodiment; FIG. 7 illustrates a first portion 700 of an automated integrated circuit representation design process, according to at least one embodiment; FIG. 8 illustrates a block diagram of a driver and/or runtime comprising one or more libraries to provide one or more application programming interfaces, according to at least one embodiment; FIG. 9A illustrates logic, according to at least one embodiment; FIG. 9B illustrates logic, according to at least one embodiment; FIG. 10 illustrates training and deployment of a neural network, according to at least one embodiment; FIG. 11 illustrates an example data center system, according to at least one embodiment; FIG. 12A illustrates an example of an autonomous vehicle, according to at least one embodiment; FIG. 12B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 12C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 12D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 13 is a block diagram illustrating a computer system, according to at least one embodiment; FIG. 14 is a block diagram illustrating a computer system, according to at least one embodiment; FIG. 15 illustrates a computer system, according to at least one embodiment; FIG. 16 illustrates a computer system, according to at least one embodiment; FIG. 17A illustrates a computer system, according to at least one embodiment; FIG. 17B illustrates a computer system, according to at least one embodiment; FIG. 17C illustrates a computer system, according to at least one embodiment; FIG. 17D illustrates a computer system, according to at least one embodiment; FIGS. 17E and 17F illustrate a shared programming model, according to at least one embodiment; FIG. 18 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment; FIGS. 19A-19B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment; FIGS. 20A-20B illustrate additional exemplary graphics processor logic according to at least one embodiment; FIG. 21 illustrates a computer system, according to at least one embodiment; FIG. 22A illustrates a parallel processor, according to at least one embodiment; FIG. 22B illustrates a partition unit, according to at least one embodiment; FIG. 22C illustrates a processing cluster, according to at least one embodiment; FIG. 22D illustrates a graphics multiprocessor, according to at least one embodiment; FIG. 23 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment; FIG. 24 illustrates a graphics processor, according to at least one embodiment; FIG. 25 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment; FI