US-20260127348-A1 - OPTIMIZATION OF MULTI-DOMAIN CLOCK GATING CIRCUITS

Abstract

Embodiments of the disclosure include a method for optimizing multi-domain clock gating circuits. The method involves associating intermediate local clock buffers to latches, the latches being associated with clock domains. The method involves clustering the intermediate local clock buffers according to connectable groups between the intermediate local clock buffers, the connectable groups supporting the clock domains. The method involves converting the connectable groups of the intermediate local clock buffers into a plurality of local clock buffers of an integrated circuit, where the plurality of local clock buffers are converted from the connectable groups according to a number of the clock domains supported by the plurality of local clock buffers.

Inventors

• William Richard Migatz
• Cindy S. Washburn

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . A computer-implemented method comprising: associating intermediate local clock buffers to latches, the latches being associated with clock domains; clustering the intermediate local clock buffers according to connectable groups between the intermediate local clock buffers, the connectable groups supporting the clock domains; and converting the connectable groups of the intermediate local clock buffers into a plurality of local clock buffers of an integrated circuit, wherein the plurality of local clock buffers are converted from the connectable groups according to a number of the clock domains supported by the plurality of local clock buffers.
2. 2 . The computer-implemented method of claim 1 , wherein the intermediate local clock buffers comprise a predefined portion of drive power of the plurality of local clock buffers.
3. 3 . The computer-implemented method of claim 1 , wherein a connectable group in the connectable groups includes the intermediate local clock buffers that are convertible to a local clock buffer.
4. 4 . The computer-implemented method of claim 1 , wherein the connectable groups are cliques in which each clique includes up to a predefined number of the intermediate local clock buffers.
5. 5 . The computer-implemented method of claim 1 , further comprising executing a weighted set covering algorithm to find a set of the connectable groups to account for all of the intermediate local clock buffers.
6. 6 . The computer-implemented method of claim 5 , wherein each connectable group in the set of the connectable groups is converted to one of the plurality of local clock buffers.
7. 7 . The computer-implemented method of claim 1 , wherein a first type of the plurality of local clock buffers supports a first number of the clock domains.
8. 8 . The computer-implemented method of claim 7 , wherein a second type of the plurality of local clock buffers supports a second number of the clock domains, the second number being less than the first number.
9. 9 . The computer-implemented method of claim 7 , wherein: a second type of the plurality of local clock buffers supports a second number of the clock domains, the second number being less than the first number; and a third type of the plurality of local clock buffers supports a third number of the clock domains, the third number being less than the second number.
10. 10 . A system comprising: a memory comprising computer readable instructions; and a processing device for executing the computer readable instructions, the computer readable instructions controlling the processing device to perform operations comprising: associating intermediate local clock buffers to latches, the latches being associated with clock domains; clustering the intermediate local clock buffers according to connectable groups between the intermediate local clock buffers, the connectable groups supporting the clock domains; and converting the connectable groups of the intermediate local clock buffers into a plurality of local clock buffers of an integrated circuit, wherein the plurality of local clock buffers are converted from the connectable groups according to a number of the clock domains supported by the plurality of local clock buffers.
11. 11 . The system of claim 10 , wherein the intermediate local clock buffers comprise a predefined portion of drive power of the plurality of local clock buffers.
12. 12 . The system of claim 10 , wherein a connectable group in the connectable groups includes the intermediate local clock buffers that are convertible to a local clock buffer.
13. 13 . The system of claim 10 , wherein the connectable groups are cliques in which each clique includes up to a predefined number of the intermediate local clock buffers.
14. 14 . The system of claim 10 , wherein the operations further comprise executing a weighted set covering algorithm to find a set of the connectable groups to account for all of the intermediate local clock buffers.
15. 15 . The system of claim 14 , wherein each connectable group in the set of the connectable groups is converted to one of the plurality of local clock buffers.
16. 16 . The system of claim 10 , wherein a first type of the plurality of local clock buffers supports a first number of the clock domains.
17. 17 . The system of claim 16 , wherein a second type of the plurality of local clock buffers supports a second number of the clock domains, the second number being less than the first number.
18. 18 . The system of claim 16 , wherein: a second type of the plurality of local clock buffers supports a second number of the clock domains, the second number being less than the first number; and a third type of the plurality of local clock buffers supports a third number of the clock domains, the third number being less than the second number.
19. 19 . A computer program product comprising: a set of one or more computer-readable storage media; program instructions, collectively stored in the set of one or more storage media, for causing a processor set to perform computer operations: associating intermediate local clock buffers to latches, the latches being associated with clock domains; clustering the intermediate local clock buffers according to connectable groups between the intermediate local clock buffers, the connectable groups supporting the clock domains; and converting the connectable groups of the intermediate local clock buffers into a plurality of local clock buffers of an integrated circuit, wherein the plurality of local clock buffers are converted from the connectable groups according to a number of the clock domains supported by the plurality of local clock buffers.
20. 20 . The computer program product of claim 19 , wherein the intermediate local clock buffers comprise a predefined portion of drive power of the plurality of local clock buffers.

Description

BACKGROUND Power consumption in integrated circuits has become an increasingly important consideration in modern electronic device design. As the demand for more powerful and energy-efficient devices continues to grow, designers may face challenges in accurately modeling and analyzing power consumption, particularly in complex circuits with multiple clock domains. Traditional clock gating techniques may be used to reduce power consumption by selectively disabling portions of a circuit when they are not in use. However, these techniques may have limitations when applied to circuits with numerous small clock gated domains. In such cases, using standard Local Clock Buffers (LCBs) for each domain may result in a large number of underloaded LCBs, potentially leading to inefficient power usage. To address this issue, multi-domain clock gating circuits, such as Micro Clock Gating LCBs (MCG LCBs), may be implemented. These circuits may allow a single LCB to drive multiple domains, with additional enable signals for separate control of each domain. While this approach may offer potential power savings, it may also introduce new challenges in analysis and circuit design. SUMMARY Embodiments of the disclosure include a method for performing circuit design optimization for an integrated circuit. The method includes associating intermediate local clock buffers to latches, the latches being associated with clock domains. Also, the method includes clustering the intermediate local clock buffers according to connectable groups between the intermediate local clock buffers, the connectable groups supporting the clock domains. Further, the method includes converting the connectable groups of the intermediate local clock buffers into a plurality of local clock buffers of an integrated circuit, wherein the plurality of local clock buffers are converted from the connectable groups according to a number of the clock domains supported by the plurality of local clock buffers. Embodiments of the disclosure include a system having a memory having computer readable instructions and a processing device for executing the computer readable instructions, the computer readable instructions controlling the processing device to perform operations. The operations include associating intermediate local clock buffers to latches, the latches being associated with clock domains. Also, the operations include clustering the intermediate local clock buffers according to connectable groups between the intermediate local clock buffers, the connectable groups supporting the clock domains. Further, the operations include converting the connectable groups of the intermediate local clock buffers into a plurality of local clock buffers of an integrated circuit, wherein the plurality of local clock buffers are converted from the connectable groups according to a number of the clock domains supported by the plurality of local clock buffers. Embodiments of the disclosure also include a computer program product for circuit design optimization. The computer program product has a set of one or more computer-readable storage media and program instructions, collectively stored in the set of one or more storage media, for causing a processor set to perform computer operations. The operations include associating intermediate local clock buffers to latches, the latches being associated with clock domains. Also, the operations include clustering the intermediate local clock buffers according to connectable groups between the intermediate local clock buffers, the connectable groups supporting the clock domains. Further, the operations include converting the connectable groups of the intermediate local clock buffers into a plurality of local clock buffers of an integrated circuit, wherein the plurality of local clock buffers are converted from the connectable groups according to a number of the clock domains supported by the plurality of local clock buffers. Embodiments of the disclosure include a method for optimizing an integrated circuit. The method includes associating intermediate local clock buffers to latches, the latches being associated with clock domains. Also, the method includes creating a graph of the intermediate local clock buffers in which the intermediate local clock buffers are vertices and the vertices are connected by edges, the edges representing the intermediate local clock buffers that are mergeable. The method includes clustering the intermediate local clock buffers in the graph according to cliques, the cliques supporting clock domains. Further, the method includes converting the cliques of the intermediate local clock buffers into a plurality of local clock buffers of the integrated circuit, wherein the plurality of local clock buffers are converted from the cliques according to a number of the clock domains supported by the plurality of local clock buffers. Embodiments of the disclosure include a system having a memory having computer readable