US-20260127350-A1 - FRONT-END-OF-LINE FLOORPLAN OF INTEGRATED CIRCUIT THAT HAS DUMMIES INSERTED BY BLOCKAGE-AIDED DUMMY INSERTION AND RELATED METHOD

US20260127350A1US 20260127350 A1US20260127350 A1US 20260127350A1US-20260127350-A1

Abstract

A front-end-of-line (FEOL) floorplan of an integrated circuit includes a plurality of FEOL components, a non-rectangle-shaped empty region, a first FEOL dummy, and a second FEOL dummy. The non-rectangle-shaped empty region is located between the FEOL components, and includes a first empty region in a first direction and a second empty region in a second direction perpendicular to the first direction, where the first empty region has a first end connected to the second empty region. The first FEOL dummy is inserted in the first empty region. The second FEOL dummy is inserted in the second empty region. The first FEOL dummy is separated from the second FEOL dummy at the first end of the first empty region.

Inventors

Yi-Chun Tsai
Shao-Hua Huang
Wei-Min HSU
Chi-hsin Chang
Vanessa Kim Ann Sim
Shih-Yu Lin
Kin Hooi Dia
Jen-Hang Yang
Siaw Fuang Pua
Yi-Te Chiu
Yi Guo
Hsu-Hua Liu
Shuyuan Zhang
Chieh-Jou Cheng
Kian Loo Wong
Yi-Ping Chang
Yi-Jung Chen
Szu-Ying Chen

Assignees

MEDIATEK INC.

Dates

Publication Date: 20260507
Application Date: 20251106

Claims (17)

1 . A front-end-of-line (FEOL) floorplan of an integrated circuit comprising: a plurality of FEOL components; a non-rectangle-shaped empty region, located between the plurality of FEOL components, wherein the non-rectangle shaped empty region comprises: a first empty region, in a first direction; and a second empty region, in a second direction perpendicular to the first direction, wherein the first empty region has a first end connected to the second empty region; a first FEOL dummy, inserted in the first empty region; and a second FEOL dummy, inserted in the second empty region, wherein the first FEOL dummy is separated from the second FEOL dummy at the first end of the first empty region.
2 . The FEOL floorplan of claim 1 , wherein the first empty region has a minimum width specified by design rules of a semiconductor foundry.
3 . The FEOL floorplan of claim 1 , wherein the second empty region has a minimum width specified by design rules of a semiconductor foundry.
4 . The FEOL floorplan of claim 1 , wherein the first FEOL dummy is separated from the second FEOL dummy by an FEOL blockage defined at the first end of the first empty region.
5 . The FEOL floorplan of claim 1 , wherein the non-rectangle shaped empty region further comprises: a third empty region, in the first direction, wherein the third empty region has a first end connected to the second empty region; and the FEOL floorplan further comprises: a third FEOL dummy, inserted in the third empty region, wherein the third FEOL dummy is separated from the second FEOL dummy at the first end of the third empty region.
6 . The FEOL floorplan of claim 1 , wherein the first FEOL dummy is an oxide diffusion (OD) dummy, a poly (PO) dummy, or a Cut Poly (CPO) dummy.
7 . The FEOL floorplan of claim 1 , wherein the second FEOL dummy is an oxide diffusion (OD) dummy, a poly (PO) dummy, or a Cut Poly (CPO) dummy.
8 . The FEOL floorplan of claim 1 , wherein the first direction is a horizontal direction of the FEOL floorplan, and the second direction is a vertical direction of the FEOL floorplan.
9 . The FEOL floorplan of claim 1 , wherein the first direction is a vertical direction of the FEOL floorplan, and the second direction is a horizontal direction of the FEOL floorplan.
10 . A method of designing a front-end-of-line (FEOL) floorplan of an integrated circuit comprising: defining a plurality of FEOL components in the FEOL floorplan, wherein a non-rectangle-shaped empty region is located between the plurality of FEOL components, and comprises: a first empty region, in a first direction; and a second empty region, in a second direction perpendicular to the first direction, wherein the first empty region has a first end connected to the second empty region; defining a first FEOL blockage at the first end of the first empty region; and running a dummy insertion utility to automatically insert a first FEOL dummy and a second FEOL dummy, wherein the first FEOL blockage assists the dummy insertion utility in inserting the first FEOL dummy in the first empty region only.
11 . The method of claim 10 , wherein the first empty region has a minimum width specified by design rules of a semiconductor foundry.
12 . The method of claim 10 , wherein the second empty region has a minimum width specified by design rules of a semiconductor foundry.
13 . The method of claim 10 , wherein the non-rectangle shaped empty region further comprises: a third empty region, in the first direction, wherein the third empty region has a first end connected to the second empty region; and the method further comprises: defining a second FEOL blockage at the first end of the third empty region; and running the dummy insertion utility to automatically insert a third FEOL dummy, wherein the second FEOL blockage assists the dummy insertion utility in inserting the third FEOL dummy in the third empty region only.
14 . The method of claim 10 , wherein the first FEOL dummy is an oxide diffusion (OD) dummy, a poly (PO) dummy, or a Cut Poly (CPO) dummy.
15 . The method of claim 10 , wherein the second FEOL dummy is an oxide diffusion (OD) dummy, a poly (PO) dummy, or a Cut Poly (CPO) dummy.
16 . The method of claim 10 , wherein the first direction is a horizontal direction of the FEOL floorplan, and the second direction is a vertical direction of the FEOL floorplan.
17 . The method of claim 10 , wherein the first direction is a vertical direction of the FEOL floorplan, and the second direction is a horizontal direction of the FEOL floorplan.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/717,829, filed on November 7th, 2024. The content of the application is incorporated herein by reference. BACKGROUND The present invention relates to an integrated circuit (IC) design, and more particularly, to a front-end-of-line (FEOL) floorplan of an IC that has FEOL dummies inserted by blockage-aided FEOL dummy insertion and a related method. IC fabrication is a complex semiconductor process during which electronic circuits are created in and on a wafer. The semiconductor process is a multiple-step sequence which can be divided into two major processing stages, namely an FEOL process and a back-end-of-line (BEOL) process. The FEOL process refers to the construction of the components (e.g., transistors) of the IC directly inside the wafer. Specifically, the FEOL process focuses on forming electronic device structures that define IC's basic functions. Since the FEOL process is the first stage of the semiconductor process, it sets the foundation for the subsequent stages, including the BEOL process. Specifically, once all the components of the IC are ready, the BEOL process is performed to deposit the metal wiring between the individual components in order to interconnect them. After the BEOL process, a back-end process (also called post-fab process) is performed, which includes wafer testing, die separation, die testing, IC packaging, and final testing. An FEOL floorplan of an IC includes a plurality of FEOL components. For example, an FEOL component may be a macro, a static random access memory (SRAM), an intellectual property (IP) cell, or a standard cell region. It is possible that FEOL components with different dimensions (e.g., different widths and/or different heights) may be included in the FEOL floorplan, resulting in a non-rectangle shaped empty region (e.g., a Z-shaped empty region) between non-identical FEOL components. When the non-rectangle shaped empty region has a minimum horizontal/vertical width specified by design rules of a semiconductor foundry, a dummy insertion utility provided by the semiconductor foundry has dummy insertion utility limitations, and may have difficult in inserting horizontal/vertical dummies into the non-rectangle shaped empty region. In other words, dummy insertion cannot work in the non-rectangle shaped empty region with minimum spacing, which causes design rule checking (DRC) violation. One conventional approach is to redo the FEOL floorplan to enlarge the empty region for accommodating FEOL dummies inserted by the dummy insertion utility provided by the semiconductor foundry. After the designer enlarges the empty region by redoing the FEOL floorplan, he/she needs to redo placement, clock tree synthesis (CTS), routing, and physical verification (PV) again. As a result, the conventional approach increases the die area as well as the time to market. SUMMARY One of the objectives of the claimed invention is to provide an FEOL floorplan of an IC that has a non-rectangle shaped empty region with FEOL dummies inserted by blockage-aided FEOL dummy insertion and a related method. According to a first aspect of the present invention, an exemplary FEOL floorplan of an integrated circuit is disclosed. The exemplary FEOL floorplan includes a plurality of FEOL components, a non-rectangle-shaped empty region, a first FEOL dummy, and a second FEOL dummy. The non-rectangle-shaped empty region is located between the plurality of FEOL components, and includes a first empty region in a first direction and a second empty region in a second direction perpendicular to the first direction, wherein the first empty region has a first end connected to the second empty region. The first FEOL dummy is inserted in the first empty region. The second FEOL dummy is inserted in the second empty region. The first FEOL dummy is separated from the second FEOL dummy at the first end of the first empty region. According to a second aspect of the present invention, an exemplary method of designing an FEOL floorplan of an integrated circuit is disclosed. The exemplary method includes: defining a plurality of FEOL components in the FEOL floorplan, wherein a non-rectangle-shaped empty region is located between the plurality of FEOL components, and includes a first empty region in a first direction and a second empty region in a second direction perpendicular to the first direction, wherein the first empty region has a first end connected to the second empty region; placing a first FEOL blockage at the first end of the first empty region; and running a dummy insertion utility to automatically insert a first FEOL dummy and a second FEOL dummy, wherein the first FEOL blockage assists the dummy insertion utility in inserting the first FEOL dummy in the first empty region only. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art a