US-20260127351-A1 - SIMULATION MODEL STABILITY DETERMINATION METHOD

US20260127351A1US 20260127351 A1US20260127351 A1US 20260127351A1US-20260127351-A1

Abstract

A grid dependency check for a simulation model is described. According to embodiments, a grid dependency check can be advantageously performed faster and more efficiently compared to prior grid dependency checks. Certain portions of a design layout are selected and cropped to a minimum size required by the model, and used to generate a second design layout. The selected portions are rotated and/or shifted relative to the grid to form one or more moved portions. The second design layout includes the one or more selected portions and the one or more moved portions so that a modeling operation (e.g., model apply) needs to only run a single time instead of multiple times as in prior grid dependency checks.

Inventors

Jiaxing REN
Yi-Yin Chen
Yongfa Fan
Jiao LIANG

Assignees

ASML NETHERLANDS B.V.

Dates

Publication Date: 20260507
Application Date: 20221024

Claims (20)

1 . A non-transitory computer readable medium having instructions thereon or therein, the instructions, when executed by one or more processors, configured to cause the one or more processors to at least: extract one or more selected portions of a first pattern layout, the first pattern layout overlaid on a grid; move the one or more selected portions relative to the grid to form one or more moved portions; generate a second pattern layout comprising the one or more selected portions and the one or more moved portions; and provide the second pattern layout to a simulation model to determine one or more predicted characteristics for the one or more selected portions and the one or more moved portions.
2 . The medium of claim 1 , wherein the instructions are further configured to cause the one or more processors to determine a stability of the simulation model based on the one or more predicted characteristics.
3 . The medium of claim 2 , wherein the instructions configured to cause the one or processors to determine the stability are further configured to cause the one or more processors to determine one or more predicted characteristics associated with the one or more selected portions and the one or more moved portions with the simulation model based on the second pattern layout.
4 . The medium of claim 2 , wherein the instructions configured to cause the one or processors to determine the stability are further configured to cause the one or more processors to perform a grid dependency (GD) check of the simulation model.
5 . The medium of claim 1 , wherein a predicted characteristic comprises a predicted image and/or a predicted geometry for the second pattern layout.
6 . The medium of claim 5 , wherein the predicted characteristic comprises the predicted image and wherein the instructions configured to cause the one or processors to determine the one or more predicted characteristics are further configured to cause the one or more processors to generate the predicted image, the predicted image comprising a resist image, and the one or more predicted characteristics are derived from the predicted image.
7 . The medium of claim 5 , wherein the predicted characteristic comprises the predicted geometry, and the predicted geometry comprises an etch contour.
8 . The medium of claim 1 , wherein a predicted characteristic comprises a predicted critical dimension (CD) for the second pattern layout.
9 . The medium of claim 8 , wherein the predicted characteristic comprises a plurality of critical dimensions predicted by the simulation model for the one or more selected portions and the one or more moved portions in the second pattern layout, and wherein the instructions configured to cause the one or processors to determine the stability are further configured to cause the one or more processors to determine the stability based on a range of the plurality of critical dimensions.
10 . The medium of claim 1 , wherein the instructions configured to cause the one or processors to move the one or more selected portions relative to the grid are further configured to cause the one or more processors to rotate and/or shift the one or more selected portions relative to the grid.
11 . The medium of claim 1 , wherein a size of the one or more selected portions is determined based on simulation model erosion.
12 . The medium of claim 1 , wherein the pattern layout comprises a design layout for a semiconductor manufacturing process, and wherein the simulation model comprises a lithography simulation model.
13 . The medium of claim 12 , wherein a selected portion has a first dimension for an extreme ultraviolet (EUV) semiconductor manufacturing process, or a second, larger dimension, for a deep ultraviolet (DUV) semiconductor manufacturing process.
14 . The medium of claim 1 , wherein the simulation model is configured for an optical proximity correction (OPC) process, and wherein the one or more selected portions have a smaller dimensional size than portions used by the simulation model in the OPC process.
15 . The medium of claim 1 , wherein the instructions further cause the one or more processors to electronically access the first pattern layout, the first pattern layout comprising a graphic design system (.GDS) or OASIS file.
16 . A non-transitory computer readable medium having instructions thereon or therein, the instructions, when executed by a computer system, configured to cause the computer system to at least: electronically access a first design layout for a semiconductor manufacturing process, the first design layout overlaid on a grid; extract one or more selected portions of the first design layout; rotate and/or shift the one or more selected portions relative to the grid to form one or more moved portions; generate a second design layout comprising the one or more selected portions and the one or more moved portions; use a lithography simulation model to determine one or more predicted results for the one or more selected portions and the one or more moved portions based on the second design layout; and perform a grid dependency check for the simulation model based on the one or more predicted results, wherein the grid dependency of the simulation model is indicated by variation in the one or more predicted results caused by positions of the one or more selected portions and the one or more moved portions in the second design layout relative to the grid.
17 . The medium of claim 16 , wherein a predicted result comprises a predicted resist image, a predicted etch contour, and/or a predicted critical dimension (CD) for the second design layout.
18 . The medium of claim 16 , wherein a predicted result comprises a plurality of critical dimensions from different ones of the one or more selected portions and the one or more moved portions in the second design layout, and wherein the grid dependency check of the simulation model is based on a range of the plurality of critical dimensions.
19 . The medium of claim 16 , wherein a size of the one or more selected portions is minimized based on simulation model erosion.
20 . The medium of claim 16 , wherein the simulation model is configured for an optical proximity correction (OPC) process, and wherein the one or more selected portions have a smaller dimensional size than portions used by the simulation model in the OPC process.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority of U.S. application 63/281,228 which was filed on Nov. 19, 2021 and which is incorporated herein in its entirety by reference. TECHNICAL FIELD The present disclosure relates generally to determining simulation model stability associated with computational lithography. BACKGROUND A lithographic projection apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A patterning device (e.g., a mask) may include or provide a pattern corresponding to an individual layer of the IC (“design layout”), and this pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the pattern on the patterning device. In general, a single substrate contains a plurality of adjacent target portions to which the pattern is transferred successively by the lithographic projection apparatus, one target portion at a time. In one type of lithographic projection apparatus, the pattern on the entire patterning device is transferred onto one target portion in one operation. Such an apparatus is commonly referred to as a stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, a projection beam scans over the patterning device in a given reference direction (the “scanning” direction) while synchronously moving the substrate parallel or anti-parallel to this reference direction. Different portions of the pattern on the patterning device are transferred to one target portion progressively. Since, in general, the lithographic projection apparatus will have a reduction ratio M (e.g., 4), the speed F at which the substrate is moved will be 1/M times that at which the projection beam scans the patterning device. More information with regard to lithographic devices can be found in, for example, U.S. Pat. No. 6,046,792, incorporated herein by reference. Prior to transferring the pattern from the patterning device to the substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures (“post-exposure procedures”), such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the transferred pattern. This array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish the individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by a technique such as dicing or sawing, such that the individual devices can be mounted on a carrier, connected to pins, etc. Manufacturing devices, such as semiconductor devices, typically involves processing a substrate (e.g., a semiconductor wafer) using a number of fabrication processes to form various features and multiple layers of the devices. Such layers and features are typically manufactured and processed using, e.g., deposition, lithography, etch, chemical-mechanical polishing, and ion implantation. Multiple devices may be fabricated on a plurality of dies on a substrate and then separated into individual devices. This device manufacturing process may be considered a patterning process. A patterning process involves a patterning step, such as optical and/or nanoimprint lithography using a patterning device in a lithographic apparatus, to transfer a pattern on the patterning device to a substrate and typically, but optionally, involves one or more related pattern processing steps, such as resist development by a development apparatus, baking of the substrate using a bake tool, etching using the pattern using an etch apparatus, etc. Lithography is a central step in the manufacturing of device such as ICs, where patterns formed on substrates define functional elements of the devices, such as microprocessors, memory chips, etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electro mechanical systems (MEMS) and other devices. As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continually been reduced. At the same time, the number of functional elements, such as transistors, per device has been steadily increasing, following a trend commonly referred to as “Moore's law.” At the current state of technology, layers of devices are manufactured using lithographic projection apparatuses that project a design layout onto a substrate using illuminat