US-20260127422-A1 - BIAS CURRENT GENERATION CIRCUIT COMPRISING SELF-CORRECTION CIRCUIT, APPARATUS COMPRISING SPIKE NEURAL NETWORK DRIVEN BASED THEREON, AND METHOD FOR CORRECTING BIAS CURRENT

US20260127422A1US 20260127422 A1US20260127422 A1US 20260127422A1US-20260127422-A1

Abstract

An apparatus comprises a bias current generation circuit configured to generate a bias current, a synapse circuit including a weight register storing a weight value and configured to perform a charge operation based on the input spike signal, the bias current, and the weight value, a membrane capacitor having a potential determined based on the charge operation of the synapse circuit, and a neuron circuit configured to generate an output spike signal based on a comparison between the potential of the membrane capacitor and a threshold potential. The bias current generation circuit comprises a self-correction circuit, and the self-correction circuit comprises a target input spike register storing a value related to a target number of input spikes and is configured to correct the bias current generated by the bias current generation circuit based on the value related to the target number of input spikes.

Inventors

Kwang Il Oh
Hyuk Kim
Jae-Jin Lee

Assignees

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Dates

Publication Date: 20260507
Application Date: 20251027
Priority Date: 20241106

Claims (20)

1 . An apparatus comprising a spiking neural network circuit configured to generate an output spike signal based on an input spike signal received from an axon line, the apparatus comprising: a bias current generation circuit configured to generate a bias current; a synapse circuit including a weight register storing a weight value and configured to perform a charge operation based on the input spike signal, the bias current, and the weight value; a membrane capacitor having a potential determined based on the charge operation of the synapse circuit; and a neuron circuit configured to generate a first output spike signal based on a comparison between the potential of the membrane capacitor and a threshold potential, wherein the bias current generation circuit comprises a self-correction circuit, wherein the self-correction circuit comprises a target input spike register storing a value related to a target number of input spikes, and wherein the self-correction circuit is configured to correct the bias current generated by the bias current generation circuit based on the value related to the target number of input spikes.
2 . The apparatus of claim 1 , wherein the neuron circuit is configured to generate the first output spike signal based on a comparison result indicating that the potential of the membrane capacitor is lower than the threshold potential.
3 . The apparatus of claim 1 , wherein the self-correction circuit is configured to output a binary code for correcting the bias current.
4 . The apparatus of claim 1 , wherein the self-correction circuit comprises: a replica synapse circuit configured to receive the input spike signal from the axon line and to perform a charge operation; a replica membrane capacitor having a potential determined based on the charge operation of the replica synapse circuit; a replica neuron circuit configured to generate a second output spike signal based on the potential of the replica membrane capacitor; an input spike counter configured to receive the input spike signal from the axon line and the second output spike signal from the replica neuron circuit, and to count a number of spikes in the input spike signal until the second output spike signal is generated; a comparator configured to compare the counted number of spikes with the target number of input spikes; and a binary code bit controller configured to modify the binary code based on a comparison result of the comparator.
5 . The apparatus of claim 4 , wherein the binary code bit controller is configured to modify the binary code by increasing a least significant bit within upper bits of the binary code by one bit based on a comparison result indicating that the counted number of spikes is less than the target number of input spikes.
6 . The apparatus of claim 4 , wherein the binary code bit controller is configured to modify the binary code by decreasing a least significant bit within lower bits of the binary code by one bit based on a comparison result indicating that the counted number of spikes is greater than the target number of input spikes.
7 . The apparatus of claim 4 , wherein the binary code bit controller stores a predetermined initial binary code, wherein the replica neuron circuit generates the second output spike signal based on a first bias current corresponding to the initial binary code, wherein the input spike counter counts the number of spikes in the input spike signal until the second output spike signal is generated, wherein the comparator compares the counted number of spikes with the target number of input spikes, and wherein the binary code bit controller modifies the initial binary code to a first binary code by increasing a least significant bit within upper bits of the initial binary code by one bit based on a comparison result indicating that the counted number of spikes is less than the target number of input spikes.
8 . The apparatus of claim 4 , wherein the input spike counter resets a count value when the second output spike signal is generated by the replica neuron circuit.
9 . The apparatus of claim 4 , wherein the self-correction circuit is configured to terminate a correction procedure of the bias current based on a comparison result of the comparator indicating that the number of spikes of the input spike signal counted by the input spike counter is equal to the target number of input spikes.
10 . The apparatus of claim 1 , wherein the bias current generation circuit comprises a current correction path connected to the self-correction circuit, and a synapse bias path through which a bias current provided to the spiking neural network flows, wherein the current correction path and the synapse bias path are formed of a same current mirror including transistors, and wherein a magnitude of a current flowing through the current correction path is equal to a magnitude of a current flowing through the synapse bias path.
11 . A bias current generation circuit configured to provide a bias current to a spiking neural network circuit that generates an output spike signal based on an input spike signal received from an axon line and to correct the bias current, the bias current generation circuit comprising: a first group of transistors forming a synapse bias path for providing the bias current to the spiking neural network circuit; a second group of transistors forming a current correction path and configured as a same current mirror as the first group of transistors; a third group of transistors including transistors for controlling the bias current; and a self-correction circuit configured to provide a control signal corresponding to a binary code for correcting the bias current to the third group of transistors, wherein the self-correction circuit comprises: a replica synapse circuit configured to receive the input spike signal from the axon line and to perform a charge operation; a replica membrane capacitor having a potential determined based on the charge operation of the replica synapse circuit; a replica neuron circuit configured to generate an output spike signal based on the potential of the replica membrane capacitor; an input spike counter configured to receive the input spike signal from the axon line and the output spike signal from the replica neuron circuit, and to count a number of spikes in the input spike signal until the output spike signal is generated; a target input spike register configured to store a value related to a target number of input spikes; a comparator configured to compare the counted number of spikes with the target number of input spikes; and a binary code bit controller configured to modify the binary code based on a comparison result of the comparator.
12 . The bias current generation circuit of claim 11 , wherein the binary code bit controller is configured to modify the binary code by increasing a least significant bit within upper bits of the binary code by one bit based on a comparison result indicating that the counted number of spikes is less than the target number of input spikes.
13 . The bias current generation circuit of claim 11 , wherein the binary code bit controller is configured to modify the binary code by decreasing a least significant bit within lower bits of the binary code by one bit based on a comparison result indicating that the counted number of spikes is greater than the target number of input spikes.
14 . The bias current generation circuit of claim 11 , wherein the binary code bit controller stores a predetermined initial binary code, wherein the replica neuron circuit generates the output spike signal based on a first bias current corresponding to the initial binary code, wherein the input spike counter counts the number of spikes in the input spike signal until the output spike signal is generated, wherein the comparator compares the counted number of spikes with the target number of input spikes, and wherein the binary code bit controller modifies the initial binary code to a first binary code by increasing a least significant bit within upper bits of the initial binary code by one bit based on a comparison result indicating that the counted number of spikes is less than the target number of input spikes.
15 . The bias current generation circuit of claim 11 , wherein the input spike counter resets a count value when the output spike signal is generated by the replica neuron circuit.
16 . The bias current generation circuit of claim 11 , wherein the self-correction circuit is configured to terminate a correction procedure of the bias current based on a comparison result of the comparator indicating that the number of spikes of the input spike signal counted by the input spike counter is equal to the target number of input spikes.
17 . A method for correcting a bias current provided to a spiking neural network circuit configured to generate an output spike signal based on an input spike signal from an axon line, the method comprising: receiving, by a replica synapse circuit and an input spike counter, the input spike signal from the axon line; receiving, by the input spike counter, the output spike signal generated by a replica neuron circuit based on the input spike signal and a bias current corresponding to a binary code; counting, by the input spike counter, a number of spikes of the input spike signal until the output spike signal is generated; comparing, by a comparator, the counted number of spikes with a target number of input spikes; and modifying, by a binary code bit controller, the binary code based on a comparison result.
18 . The method of claim 17 , wherein modifying the binary code based on the comparison result comprises modifying the binary code by increasing a least significant bit within upper bits of the binary code by one bit based on a comparison result indicating that the counted number of spikes is less than the target number of input spikes.
19 . The method of claim 17 , wherein modifying the binary code based on the comparison result comprises modifying the binary code by decreasing a least significant bit within lower bits of the binary code by one bit based on a comparison result indicating that the counted number of spikes is greater than the target number of input spikes.
20 . The method of claim 17 , wherein the method further comprises: generating, by the replica neuron circuit, the output spike signal based on a first bias current corresponding to a predetermined initial binary code; counting, by the input spike counter, a number of spikes of the input spike signal until the output spike signal is generated; comparing, by the comparator, the counted number of spikes with a target number of input spikes; and modifying the initial binary code to a first binary code by increasing a least significant bit within upper bits of the initial binary code by one bit based on a comparison result indicating that the counted number of spikes is less than the target number of input spikes.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0156305 filed on November 6, 2024 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND The present disclosure relates to a spiking neural network circuit, and more particularly, to a bias current generation circuit comprising a self-correction circuit, an apparatus comprising a spiking neural network driven based on the bias current generation circuit, and a method for correcting a bias current. An artificial neural network (ANN) can process data or information in a manner similar to that of a biological neural network. Unlike a perceptron-based or convolution-based neural network, in a spiking neural network (SNN), a signal of a specific level is not transmitted continuously; instead, a spike signal including pulses that toggle for a short duration is transmitted. A spiking neural network circuit may be implemented using semiconductor devices. However, when implemented as a semiconductor circuit, the spiking neural network circuit may be affected by environmental factors (for example, temperature, humidity, or changes in supply voltage), which can cause errors in the computational results of the spiking neural network. Therefore, there is a need for a spiking neural network circuit capable of self-correction that compensates for variations in environmental conditions after the circuit has been fabricated. SUMMARY An object of the present disclosure is to provide a bias current generation circuit comprising a self-correction circuit, an apparatus comprising a spiking neural network driven based on the bias current generation circuit, and a method for correcting a bias current. According to an embodiment of the present disclosure, an apparatus may include a bias current generation circuit configured to generate a bias current, a synapse circuit including a weight register storing a weight value and configured to perform a charge operation based on an input spike signal, the bias current, and the weight value, a membrane capacitor having a potential determined based on the charge operation of the synapse circuit, and a neuron circuit configured to generate a first output spike signal based on a comparison between the potential of the membrane capacitor and a threshold potential. The bias current generation circuit includes a self-correction circuit, which includes a target input spike register, and the self-correction circuit corrects the bias current generated by the bias current generation circuit based on a value related to a target number of input spikes stored in the target input spike register. In one embodiment, the bias current generation circuit may include a first group of transistors forming a synapse bias path for providing the bias current to the spiking neural network circuit, a second group of transistors forming a current correction path configured as a same current mirror as the first group of transistors, a third group of transistors for controlling the bias current, and a self-correction circuit configured to provide a control signal corresponding to a binary code for correcting the bias current to the third group of transistors. In an example, the self-correction circuit may include a replica synapse circuit configured to receive an input spike signal from an axon line and perform a charge operation, a replica membrane capacitor having a potential determined based on the charge operation of the replica synapse circuit, a replica neuron circuit configured to generate an output spike signal based on the potential of the replica membrane capacitor, an input spike counter configured to receive the input spike signal from the axon line and the output spike signal from the replica neuron circuit, and to count the number of spikes of the input spike signal until the output spike signal is generated, a target input spike register configured to store a value related to a target number of input spikes, a comparator configured to compare the counted number of spikes with the target number of input spikes, and a binary code bit controller configured to modify the binary code based on the comparison result. In one embodiment, a method for correcting a bias current provided to a spiking neural network circuit may include receiving, by a replica synapse circuit and an input spike counter, an input spike signal from an axon line, receiving, by the input spike counter, an output spike signal generated by a replica neuron circuit based on the input spike signal and a bias current determined according to a binary code, counting, by the input spike counter, the number of spikes in the input spike signal until the output spike signal is generated, comparing, by a comparator, the counted number of spikes with a target number of input spikes, and modifying, by a binary code bit controller, the b