US-20260127780-A1 - COMPUTING SYSTEM PARTITION GENERATOR

Abstract

The present disclosure relates to a computing device and methods for generating graphical representation of one or more portions of a computing system. The computing device can include a computing processor and memory and configured to access configuration information identifying partitions of the computing system, wherein the computing system comprises an array of system on a wafers (SoWs), and each SoW of the array of SoWs comprises an array of dies; and generate a graphical representation of at least a portion of the computing system, wherein the graphical representation identifies the partitions and individual dies of the partitions.

Inventors

• Prateek Agrawal
• Chandrasekhar Poorna
• Ankit Jalote
• Hadi Goudarzi

Assignees

• TESLA, INC.

Dates

Publication Date

20260507

Application Date

20230928

Claims (17)

1. 1 . A computing device for generating a graphical representation of a computing system, the computing device comprising: a computing processor and a memory storing computer-executable instructions, that when executed by the computing processor, cause operations to be performed, the operations comprising: accessing configuration information identifying partitions of the computing system, wherein the computing system comprises an array of system on wafers (SoWs), and each SoW of the array of SoWs comprises an array of dies; and generating a graphical representation of at least a portion of the computing system, wherein the graphical representation identifies the partitions and individual dies of the partitions.
2. 2 . The computing device of claim 1 , wherein the graphical representation provides information associated with functionality of the individual dies of the partitions.
3. 3 . The computing device of claim 2 , wherein the information associated with functionality of individual dies of the partitions indicates whether each of the individual dies is functional, partially functional, or non-functional.
4. 4 . The computing device of claim 1 , wherein the configuration information defines a voltage supply level and a clock frequency for each of the partitions.
5. 5 . The computing device of claim 1 , wherein the operations further comprise checking for an illegal configuration of the configuration information.
6. 6 . The computing device of claim 1 , wherein the operations further comprise dynamically generating the partitions.
7. 7 . The computing device of claim 1 , wherein the operations further comprise generating a second graphical representation of dies of a partition of the partitions, and the second graphical representation indicates an error on one or more nodes of a particular die of the partition.
8. 8 . The computing device of claim 1 , further comprising a display configured to display the graphical representation.
9. 9 . A method of generating a graphical representation of a computing system, the method comprising: accessing configuration information identifying partitions of the computing system, wherein the configuration information is stored in memory, wherein the computing system comprises an array of system on wafers (SoWs), and each SoW of the array of SoWs comprises an array of dies; and generating, with a computing device, a graphical representation of at least a portion of the computing system, wherein the graphical representation identifies the partitions and individual dies of the partitions.
10. 10 . The method of claim 9 , wherein the graphical representation provides information associated with functionality of the individual dies of the partitions.
11. 11 . The method of claim 10 , wherein the information associated with functionality of individual dies of the partitions indicates whether each of the individual dies is functional, partially functional, or non-functional.
12. 12 . The method of claim 9 , wherein the configuration information defines a voltage supply level and a clock frequency for each of the partitions.
13. 13 . The method of claim 9 , further comprising checking for an illegal configuration of the configuration information.
14. 14 . The method of claim 9 , further comprising dynamically generating the partitions.
15. 15 . The method of claim 9 , further comprising generating a second graphical representation of dies of a partition of the partitions, wherein the second graphical representation indicates an error on one or more nodes of a particular die of the partition.
16. 16 . The method of claim 9 , further displaying graphical representation on a display.
17. 17 . Non-transitory computer-readable storage medium comprising instructions that, when executed by one or more processors, cause the method of claim 9 to be performed.

Description

CROSS-REFERENCE TO PRIORITY APPLICATION This application claims the benefit of priority of U.S. Provisional Application No. 63/378,029, filed Sep. 30, 2022, and titled “SYSTEM ON WAFER PARTITION GENERATOR,” the disclosure of which is hereby incorporated by reference in its entirety and for all purposes. BACKGROUND Technical Field This disclosure relates generally to partitioning and/or generating a graphical representation of a computing system. Description of Related Technology Certain computing systems can be used in and/or specifically configured for high performance computing and/or computationally intensive applications, such as neural network training, neural network inference, machine learning, artificial intelligence, complex simulations, or the like. In some applications, a computing system can be used to perform neural network training. For example, such neural network training can generate data for an autopilot system for vehicle (e.g., an automobile), other autonomous vehicle functionality, or Advanced Driving Assistance System (ADAS) functionality. In high performance computing systems, there can be a high density of processing dies. It can be desirable to analyze one or more portions of the high density of dies for analyzing and debugging the high density of dies. In computing systems with a large number of processing dies, there are technical challenges associated with analyzing and debugging the dies and the associated computing system. SUMMARY OF CERTAIN INVENTIVE ASPECTS The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some prominent features of this disclosure will now be briefly described. One aspect of this disclosure is a computing device for generating a graphical representation of a computing system. The computing device includes a computing processor and a memory storing computer-executable instructions, that when executed by the computing processor, cause operations to be performed, the operations include accessing configuration information identifying partitions of the computing system and generating a graphical representation of at least a portion of the computing system. The computing system includes an array of system on a wafers (SoWs), and each SoW of the array of SoWs comprises an array of dies. In addition, the graphical representation identifies the partitions and individual dies of the partitions. In the computing device, the graphical representation can provide information associated with functionality of the individual dies of the partitions. Additionally, the information associated with functionality of individual dies of the partitions can indicate whether each of the individual dies is functional, partially functional, or non-functional. In the computing device, the configuration information can define a voltage supply level and a clock frequency for each of the partitions. In the computing device, the operations can further include checking for an illegal configuration of the configuration information. In the computing device, the operations can further include dynamically generating the partitions. In the computing device, the operations can further include generating a second graphical representation of dies of a partition of the partitions, and the second graphical representation can indicate an error on one or more nodes of a particular die of the partition In the computing device, the computing device can include a display configured to display the graphical representation. Another aspect of this disclosure is a method of generating a graphical representation of a computing system. The method includes accessing configuration information identifying partitions of the computing system and generating a graphical representation of at least a portion of the computing system. The computing system includes an array of system on a wafers (SoWs), and each SoW of the array of SoWs comprises an array of dies. In addition, the graphical representation identifies the partitions and individual dies of the partitions. In the method, the graphical representation can provide information associated with functionality of the individual dies of the partitions. Additionally, the information associated with functionality of individual dies of the partitions can indicate whether each of the individual dies is functional, partially functional, or non-functional. In the method, the configuration information can define a voltage supply level and a clock frequency for each of the partitions. In the method, the method can further include checking for an illegal configuration of the configuration information. In the method, the method can further include dynamically generating the partitions. In the method, the method can further include generating a second graphical representation of dies of a partition of the partitions, wherein the second graphical repre