US-20260127994-A1 - SEMICONDUCTOR DEVICE AND DISPLAY PANEL

Abstract

The present disclosure provides a semiconductor device and a display panel, the semiconductor device includes an insulating substrate, at least one data input terminal, and a plurality of clock lines. By dividing a plurality of shift registers into a plurality of shift register groups, each clock line of the plurality of clock lines controls a rate of a shift register group, and compared with the case of controlling all of the shift registers through a single clock line, a rate of the shift register may be easily increased to a higher value as frequencies of a plurality of clock signals increase.

Inventors

• Ning Ge
• Chao Tian
• Fei AI

Assignees

• WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Dates

Publication Date

20260507

Application Date

20230609

Priority Date

20230531

Claims (20)

1. 1 . A semiconductor device comprising: an insulating substrate comprising a source driver, wherein the source driver comprises a plurality of shift register groups, each of the plurality of shift register groups comprises a plurality of shift registers, each of the plurality of shift registers is electrically connected to a corresponding pixel circuit through a data line; at least one data input terminal electrically connected to a first stage shift register of each of the plurality of shift register groups; and a plurality of clock lines, each of the plurality of clock lines being electrically connected to each shift register in a same one of the plurality of shift register groups.
2. 2 . The semiconductor device according to claim 1 , wherein the plurality of clock lines are configured to transmit a plurality of clock signals having a same frequency and different phases respectively.
3. 3 . The semiconductor device according to claim 1 , wherein the shift registers of the plurality of shift register groups are arranged alternately in sequence.
4. 4 . The semiconductor device according to claim 2 , wherein a clock line of the plurality of clock lines for transmitting a clock signal with a more delayed phase is electrically connected to a shift register group of the plurality of shift register groups arranged further back.
5. 5 . The semiconductor device according to claim 1 , wherein the plurality of shift register groups comprises a first shift register group and a second shift register group, and the at least one data input terminal is electrically connected to the first shift register group and the second shift register group; and the plurality of clock lines comprises a first clock line and a second clock line, the first clock line is electrically connected to one of the first shift register group or the second shift register group, and the second clock line is electrically connected to another of the first shift register group or the second shift register group.
6. 6 . The semiconductor device according to claim 5 , wherein the plurality of shift register groups comprises a first shift register and a second shift register arranged alternately in sequence, the first shift register group comprises the first shift register, and the second shift register group comprises the second shift register; and the first clock line is electrically connected to the first shift register group, the second clock line is electrically connected to the second shift register group, the first clock line is configured to transmit a first clock signal, the second clock line is configured to transmit a second clock signal, and a phase of the second clock signal is delayed from a phase of the first clock signal.
7. 7 . The semiconductor device according to claim 6 , wherein a frequency of the first clock signal is the same as a frequency of the second clock signal, and a difference between the phase of the first clock signal and the phase of the second clock signal is 180°.
8. 8 . The semiconductor device according to claim 1 , wherein the source driver further comprises signal processing modules, an input terminal of each of the signal processing modules is electrically connected to an output terminal of a shift register of the shift registers, and each of the signal processing modules outputs a corresponding data signal.
9. 9 . The semiconductor device according to claim 8 , wherein each of the signal processing modules comprises a latch, a level converter, a digital-to-analog converter, and an amplifier that is electrically connected in sequence, an input terminal of the latch is electrically connected to an output terminal of the shift register, a trigger terminal of the latch is electrically connected to a data enable line, and the amplifier is configured to output a corresponding data signal.
10. 10 . The semiconductor device according to claim 1 , wherein at least one of the at least one data input terminal and the plurality of clock lines is disposed in the insulating substrate.
11. 11 . A display panel comprising the semiconductor device according to claim 1 , wherein the data input terminal is configured to transmit a digital signal.
12. 12 . The display panel according to claim 11 , wherein the plurality of clock lines are configured to transmit a plurality of clock signals having a same frequency and different phases respectively.
13. 13 . The display panel according to claim 11 , wherein the shift registers of the plurality of shift register groups are arranged alternately in sequence.
14. 14 . The display panel according to claim 12 , wherein a clock line of the plurality of clock lines for transmitting a clock signal with a more delayed phase is electrically connected to a shift register group of the plurality of shift register groups arranged further back.
15. 15 . The display panel according to claim 11 , wherein the plurality of shift register groups comprises a first shift register group and a second shift register group, and the at least one data input terminal is electrically connected to the first shift register group and the second shift register group; and the plurality of clock lines comprises a first clock line and a second clock line, the first clock line is electrically connected to one of the first shift register group or the second shift register group, and the second clock line is electrically connected to another of the first shift register group or the second shift register group.
16. 16 . The display panel according to claim 15 , wherein the plurality of shift register groups comprises a first shift register and a second shift register arranged alternately in sequence, the first shift register group comprises the first shift register, and the second shift register group comprises the second shift register; and the first clock line is electrically connected to the first shift register group, the second clock line is electrically connected to the second shift register group, the first clock line is configured to transmit a first clock signal, the second clock line is configured to transmit a second clock signal, and a phase of the second clock signal is delayed from a phase of the first clock signal.
17. 17 . The display panel according to claim 16 , wherein a frequency of the first clock signal is the same as a frequency of the second clock signal, and a difference between the phase of the first clock signal and the phase of the second clock signal is 180°.
18. 18 . The display panel according to claim 11 , wherein the source driver further comprises signal processing modules, an input terminal of each of the signal processing modules is electrically connected to an output terminal of a shift register of the shift registers, and each of the signal processing modules outputs a corresponding data signal.
19. 19 . The display panel according to claim 18 , wherein each of the signal processing modules comprises a latch, a level converter, a digital-to-analog converter, and an amplifier that is electrically connected in sequence, an input terminal of the latch is electrically connected to an output terminal of the shift register, a trigger terminal of the latch is electrically connected to a data enable line, and the amplifier is configured to output a corresponding data signal.
20. 20 . The display panel according to claim 11 , wherein at least one of the at least one data input terminal and the plurality of clock lines is disposed in the insulating substrate.

Description

TECHNICAL FIELD The present disclosure relates to a field of display technologies, and more particularly, to a semiconductor device and a display panel. BACKGROUND With the rise of 5G, Internet of Things (IoT), automotive industries, and the like, a demand for a silicon-based integrated circuit (IC) is increasing. In addition, the cost of chips is expensive, the lack of chips or the reduction of the amount of chips core may continue. In a display panel, a source driver for providing a data signal generally exists in the form of a chip, however, a rate of the source driver is limited by a bottleneck and difficult to improve. SUMMARY The present application provides a semiconductor device and a display panel to alleviate a technical problem that a rate of a source driver is limited by a bottleneck and is difficult to improve. According to a first aspect, the present disclosure provides a semiconductor device including an insulating substrate, at least one data input terminal, and a plurality of clock lines. The insulating substrate includes a source driver. The source driver includes a plurality of shift register groups, each shift register group includes a plurality of shift registers, and each of the shift registers is electrically connected to a corresponding pixel circuit through a data line. The at least one data input terminal is electrically connected to a first stage shift register of each of the plurality of shift register groups. Each of the plurality of clock lines is electrically connected to each shift register in a same one of the plurality of shift register groups. In some embodiments, the plurality of clock lines are configured to transmit a plurality of clock signals having a same frequency and different phases respectively. In some embodiments, the shift registers of the plurality of shift register groups are arranged alternately in sequence. In some of these embodiments, a clock line of the plurality of clock lines for transmitting a clock signal with a more delayed phase is electrically connected to a shift register group of the plurality of shift register groups arranged further back. In some embodiments, the plurality of shift register groups includes a first shift register group and a second shift register group, and the at least one data input terminal is electrically connected to the first shift register group and the second shift register group. The plurality of clock lines includes a first clock line and a second clock line, the first clock line is electrically connected to one of the first shift register group or the second shift register group, and the second clock line is electrically connected to another of the first shift register group or the second shift register group. In some embodiments, the plurality of shift register groups includes a first shift register and a second shift register arranged alternately in sequence, the first shift register group includes the first shift register, and the second shift register group includes the second shift register. The first clock line is electrically connected to the first shift register group, the second clock line is electrically connected to the second shift register group, the first clock line is configured to transmit a first clock signal, the second clock line is configured to transmit a second clock signal, and a phase of the second clock signal is delayed from a phase of the first clock signal. In some embodiments, a frequency of the first clock signal is the same as a frequency of the second clock signal, and a difference between the phase of the first clock signal and the phase of the first clock signal is 180°. In some embodiments, the source driver further includes signal processing modules, an input terminal of each of the signal processing modules is electrically connected to an output terminal of a shift register of the shift registers, and each of the signal processing modules outputs a corresponding data signal. In some embodiments, each of the signal processing modules includes a latch, a level converter, a digital-to-analog converter, and an amplifier that is electrically connected in sequence, an input terminal of the latch is electrically connected to an output terminal of the shift register, a trigger terminal of the latch is electrically connected to a data enable line, and the amplifier is configured to output a corresponding data signal. In some embodiments, at least one of the at least one data input terminal and the plurality of clock lines is disposed in the insulating substrate. According to a second aspect, the present disclosure provides a display panel including the semiconductor device of at least one embodiment described above, and a data input terminal is used for transmitting a digital signal. Beneficial Effect According to the semiconductor device and the display panel provided in the present disclosure, a plurality of shift registers are divided into a plurality of shift register groups, and each