US-20260127995-A1 - GATE DRIVING CIRCUITS AND DISPLAY PANELS

US20260127995A1US 20260127995 A1US20260127995 A1US 20260127995A1US-20260127995-A1

Abstract

The present disclosure provides a gate driving circuit and a display panel. When a pull-up control module controls an electrical connection between a first voltage terminal and a second node, an inverting module disconnects an electrical connection between a low-frequency clock signal terminal and a third node in response to a potential of the second node, the inverting module controls an electrical connection between the first voltage terminal and the third node in response to a potential of a first node, and a pull-down holding module disconnects an electrical connection between the first voltage terminal and the first node in response to a potential of the third node.

Inventors

Xiaohai CHEN

Assignees

Guangzhou China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Dates

Publication Date: 20260507
Application Date: 20240218
Priority Date: 20240204

Claims (20)

1 . A gate driving circuit, comprising: an inverting module, electrically connected to a first voltage terminal, a first node, a second node, and a third node, configured to control a signal transmission between the first voltage terminal and the third node in response to a potential of the first node, and configured to control a signal transmission between a low-frequency clock signal terminal and the third node in response to a potential of the second node; a pull-down holding module, electrically connected to the first voltage terminal, the first node, and the third node, and configured to control a signal transmission between the first voltage terminal and the first node in response to a potential of the third node; and a pull-up control module, electrically connected to the first voltage terminal, the first node, and the second node, configured to pull up the potential of the first node in response to a pull-up control signal, and configured to control a signal transmission between the first voltage terminal and the second node in response to the pull-up control signal, wherein when the pull-up control module is configured to electrically connect the first voltage terminal and the second node in response to the pull-up control signal, the inverting module is configured to disconnect an electrical connection between the low-frequency clock signal terminal and the third node in response to the potential of the second node, the inverting module is also configured to control an electrical connection between the first voltage terminal and the third node in response to the potential of the first node, and the pull-down holding module is configured to disconnect an electrical connection between the first voltage terminal and the first node in response to the potential of the third node.
2 . The gate driving circuit according to claim 1 , wherein the pull-up control module comprises: a first control unit, comprising a first transistor, wherein a control terminal of the first transistor is configured to receive the pull-up control signal, an input terminal of the first transistor is electrically connected to the control terminal of the first transistor, and an output terminal of the first transistor is electrically connected to the first node; and a second control unit, comprising a second transistor, wherein a control terminal of the second transistor is configured to receive the pull-up control signal, an input terminal of the second transistor is electrically connected to the first voltage terminal, and an output terminal of the second transistor is electrically connected to the second node.
3 . The gate driving circuit according to claim 2 , wherein the inverting module comprises: a third transistor, wherein a control terminal of the third transistor is electrically connected to the low-frequency clock signal terminal, an input terminal of the third transistor is electrically connected to the control terminal of the third transistor, and an output terminal of the third transistor is electrically connected to the second node; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the second node, an input terminal of the fourth transistor is electrically connected to the low-frequency clock signal terminal, and an output terminal of the fourth transistor is electrically connected to the third node; a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the first node, an input terminal of the fifth transistor is electrically connected to the first voltage terminal, and an output terminal of the fifth transistor is electrically connected to the second node; and a sixth transistor, wherein a control terminal of the sixth transistor is electrically connected to the first node, an input terminal of the sixth transistor is electrically connected to the first voltage terminal, and an output terminal of the sixth transistor is electrically connected to the third node.
4 . The gate driving circuit according to claim 3 , wherein the pull-down holding module comprises: a seventh transistor, wherein a control terminal of the seventh transistor is electrically connected to the third node, an input terminal of the seventh transistor is electrically connected to the first voltage terminal, and an output terminal of the seventh transistor is electrically connected to the first node.
5 . The gate driving circuit according to claim 4 , wherein the pull-up control module further comprises: a third control unit, comprising an eighth transistor, wherein a control terminal of the eighth transistor is configured to receive the pull-up control signal, an input terminal of the eighth transistor is electrically connected to the first voltage terminal, and an output terminal of the eighth transistor is electrically connected to the third node.
6 . The gate driving circuit according to claim 5 , wherein the second node comprises a first sub-node and a second sub-node, and the third node comprises a third sub-node and a fourth sub-node; the low-frequency clock signal terminal comprises a first low-frequency clock signal terminal and a second low-frequency clock signal terminal; the inverting module comprises a first inverting unit and a second inverting unit; in the first inverting unit, the output terminal of the third transistor, the control terminal of the fourth transistor, and the output terminal of the fifth transistor are electrically connected to the first sub-node, the output terminal of the fourth transistor and the output terminal of the sixth transistor are electrically connected to the third sub-node, and the control terminal of the third transistor and the input terminal of the fourth transistor are electrically connected to the first low-frequency clock signal terminal; and in the second inverting unit, the output terminal of the third transistor, the control terminal of the fourth transistor, and the output terminal of the fifth transistor are electrically connected to the second sub-node, the output terminal of the fourth transistor and the output terminal of the sixth transistor are electrically connected to the fourth sub-node, and the control terminal of the third transistor and the input terminal of the fourth transistor are electrically connected to the second low-frequency clock signal terminal; the pull-down holding module comprises a first pull-down holding unit and a second pull-down holding unit, the control terminal of the seventh transistor of the first pull-down holding unit is electrically connected to the third sub-node, and the control terminal of the seventh transistor of the second pull-down holding unit is electrically connected to the fourth sub-node; the second control unit of the pull-up control module comprises a first control sub-unit and a second control sub-unit, the output terminal of the second transistor of the first control sub-unit is electrically connected to the first sub-node, and the output terminal of the second transistor of the second control sub-unit is electrically connected to the second sub-node; and the third control unit of the pull-up control module comprises a third control sub-unit and a fourth control sub-unit, the output terminal of the eighth transistor of the third control sub-unit is electrically connected to the third sub-node, and the output terminal of the eighth transistor of the fourth control sub-unit is electrically connected to the fourth sub-node.
7 . The gate driving circuit according to claim 1 , wherein the pull-down holding module comprises a ninth transistor, a control terminal of the ninth transistor is electrically connected to the third node, an input terminal of the ninth transistor is electrically connected to the first voltage terminal, and an output terminal of the ninth transistor is electrically connected to a signal output terminal of the gate driving circuit.
8 . The gate driving circuit according to claim 1 , further comprising: an output module, comprising an output transistor and a first capacitor, wherein a control terminal of the output transistor is electrically connected to the first node, an input terminal of the output transistor is electrically connected to a high-frequency clock signal terminal, and an output terminal of the output transistor is electrically connected to a signal output terminal of the gate driving circuit, and the first capacitor is in series between the first node and the signal output terminal; a pull-down control module, comprising a first pull-down transistor, wherein a control terminal of the first pull-down transistor is configured to receive a pull-down control signal, an input terminal of the first pull-down transistor is electrically connected to the first voltage terminal, and an output terminal of the first pull-down transistor is electrically connected to the first node; and a reset module, comprising a first reset transistor and a second reset transistor, wherein a control terminal of the first reset transistor and a control terminal of the second reset transistor are configured to receive a reset control signal, an input terminal of the first reset transistor and an input terminal of the second reset transistor are electrically connected to the first voltage terminal, an output terminal of the first reset transistor is electrically connected to the first node, and an output terminal of the second reset transistor is electrically connected to a signal output terminal of the gate driving circuit.
9 . The gate driving circuit according to claim 8 , wherein the pull-down control module comprises a second pull-down transistor, a control terminal of the second pull-down transistor is configured to receive the pull-down control signal, an input terminal of the second pull-down transistor is electrically connected to the first voltage terminal, and an output terminal of the second pull-down transistor is electrically connected to the signal output terminal.
10 . The gate driving circuit according to claim 8 , further comprising: a cascade transmission module, comprising a cascade transistor, wherein a control terminal of the cascade transistor is electrically connected to the first node, an input terminal of the cascade transistor is electrically connected to the high-frequency clock signal terminal, and an output terminal of the cascade transistor is electrically connected to a cascade transmission output terminal of the gate driving circuit.
11 . The gate driving circuit according to claim 10 , wherein the pull-down holding module further comprises a tenth transistor, a control terminal of the tenth transistor is electrically connected to the third node, an input terminal of the tenth transistor is electrically connected to the first voltage terminal, and an output terminal of the tenth transistor is electrically connected to the cascade transmission output terminal.
12 . The gate driving circuit according to claim 10 , wherein the reset module further comprises a third reset transistor, a control terminal of the third reset transistor is configured to receive the reset control signal, an input terminal of the third reset transistor is electrically connected to the first voltage terminal, and an output terminal of the third reset transistor is electrically connected to the cascade transmission output terminal.
13 . A display panel, comprising a gate driving unit, the gate driving unit comprising a plurality of gate driving circuits arranged in cascade, and at least one of the gate driving circuits comprising: an inverting module, electrically connected to a first voltage terminal, a first node, a second node, and a third node, configured to control a signal transmission between the first voltage terminal and the third node in response to a potential of the first node, and configured to control a signal transmission between a low-frequency clock signal terminal and the third node in response to a potential of the second node; a pull-down holding module, electrically connected to the first voltage terminal, the first node, and the third node, and configured to control a signal transmission between the first voltage terminal and the first node in response to a potential of the third node; and a pull-up control module, electrically connected to the first voltage terminal, the first node, and the second node, configured to pull up the potential of the first node in response to a pull-up control signal, and configured to control a signal transmission between the first voltage terminal and the second node in response to the pull-up control signal, wherein when the pull-up control module is configured to electrically connect the first voltage terminal and the second node in response to the pull-up control signal, the inverting module is configured to disconnect an electrical connection between the low-frequency clock signal terminal and the third node in response to the potential of the second node, the inverting module is also configured to control an electrical connection between the first voltage terminal and the third node in response to the potential of the first node, and the pull-down holding module is configured to disconnect an electrical connection between the first voltage terminal and the first node in response to the potential of the third node; and wherein an (n−4)th stage gate control signal output by an (n−4)th stage gate driving circuit serves as the pull-up control signal received by the pull-up control module of the n-th stage gate driving circuit.
14 . The display panel according to claim 13 , wherein a voltage of a low-frequency clock signal transmitted by the low-frequency clock signal terminal during a sensing phase of the display panel is less than a voltage of the low-frequency clock signal during a display phase of the display panel.
15 . The display panel according to claim 13 , comprising a plurality of sub-pixels electrically connected to the gate driving unit.
16 . The display panel according to claim 13 , wherein the pull-up control module comprises: a first transistor, wherein a control terminal of the first transistor is configured to receive the pull-up control signal, an input terminal of the first transistor is electrically connected to the control terminal of the first transistor, and an output terminal of the first transistor is electrically connected to the first node; and a second transistor, wherein a control terminal of the second transistor is configured to receive the pull-up control signal, an input terminal of the second transistor is electrically connected to the first voltage terminal, and an output terminal of the second transistor is electrically connected to the second node.
17 . The display panel according to claim 16 , wherein the inverting module comprises: a third transistor, wherein a control terminal of the third transistor is electrically connected to the low-frequency clock signal terminal, an input terminal of the third transistor is electrically connected to the control terminal of the third transistor, and an output terminal of the third transistor is electrically connected to the second node; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the second node, an input terminal of the fourth transistor is electrically connected to the low-frequency clock signal terminal, and an output terminal of the fourth transistor is electrically connected to the third node; a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the first node, an input terminal of the fifth transistor is electrically connected to the first voltage terminal, and an output terminal of the fifth transistor is electrically connected to the second node; and a sixth transistor, wherein a control terminal of the sixth transistor is electrically connected to the first node, an input terminal of the sixth transistor is electrically connected to the first voltage terminal, and an output terminal of the sixth transistor is electrically connected to the third node.
18 . The display panel according to claim 17 , wherein the pull-down holding module comprises: a seventh transistor, wherein a control terminal of the seventh transistor is electrically connected to the third node, an input terminal of the seventh transistor is electrically connected to the first voltage terminal, and an output terminal of the seventh transistor is electrically connected to the first node.
19 . The display panel according to claim 18 , wherein the pull-up control module further comprises: an eighth transistor, wherein a control terminal of the eighth transistor is configured to receive the pull-up control signal, an input terminal of the eighth transistor is electrically connected to the first voltage terminal, and an output terminal of the eighth transistor is electrically connected to the third node.
20 . The display panel according to claim 13 , wherein the at least one of the gate driving circuits further comprises: an output module, comprising an output transistor and a first capacitor, wherein a control terminal of the output transistor is electrically connected to the first node, an input terminal of the output transistor is electrically connected to a high-frequency clock signal terminal, and an output terminal of the output transistor is electrically connected to a signal output terminal of the gate driving circuit, and the first capacitor is in series between the first node and the signal output terminal; a pull-down control module, comprising a first pull-down transistor, wherein a control terminal of the first pull-down transistor is configured to receive a pull-down control signal, an input terminal of the first pull-down transistor is electrically connected to the first voltage terminal, and an output terminal of the first pull-down transistor is electrically connected to the first node; and a reset module, comprising a first reset transistor and a second reset transistor, wherein a control terminal of the first reset transistor and a control terminal of the second reset transistor are configured to receive a reset control signal, an input terminal of the first reset transistor and an input terminal of the second reset transistor are electrically connected to the first voltage terminal, an output terminal of the first reset transistor is electrically connected to the first node, and an output terminal of the second reset transistor is electrically connected to a signal output terminal of the gate driving circuit.

Description

TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, to gate driving circuits and display panels. BACKGROUND In a gate driving circuit, in order to output a required gate control signal, two transistors are generally arranged to respectively pull up and pull down a potential of a first node, so that an output transistor can in the on or off state in response to the potential of the first node. However, during a process of the output transistor changing from the off state to the on state in response to the potential of the first node, the transistor configured to pull down the potential of the first node undergoes the process of changing from the on state to the off state. Therefore, when the transistor configured to pull up the potential of the first node is used to pull up the potential of the first node, the transistor configured to pull down the potential of the first node will still maintain the on state for a certain period of time, affecting the effect of pulling up the potential of the first node, causing the gate driving circuit to have problems with temperature rise and reduced reliability. SUMMARY Embodiments of the present disclosure provide gate driving circuits and display panels, which may improve the problems of temperature rise and reduced reliability of the gate driving circuit. Embodiments of the present disclosure provide a gate driving circuit, which includes an inverting module, a pull-down holding module, and a pull-up control module. The inverting module is electrically connected to a first voltage terminal, a first node, a second node, and a third node. The inverting module is configured to control a signal transmission between the first voltage terminal and the third node in response to a potential of the first node, and configured to control a signal transmission between a low-frequency clock signal terminal and the third node in response to a potential of the second node. The pull-down holding module is electrically connected to the first voltage terminal, the first node, and the third node. The pull-down holding module is configured to control a signal transmission between the first voltage terminal and the first node in response to a potential of the third node. The pull-up control module is electrically connected to the first voltage terminal, the first node, and the second node, configured to pull up the potential of the first node in response to a pull-up control signal. The pull-up control module is configured to control a signal transmission between the first voltage terminal and the second node in response to the pull-up control signal. When the pull-up control module is configured to electrically connect the first voltage terminal and the second node in response to the pull-up control signal, the inverting module is configured to disconnect an electrical connection between the low-frequency clock signal terminal and the third node in response to the potential of the second node, the inverting module is also configured to control an electrical connection between the first voltage terminal and the third node in response to the potential of the first node, and the pull-down holding module is configured to disconnect an electrical connection between the first voltage terminal and the first node in response to the potential of the third node. The present disclosure also provides a display panel, including a gate driving unit. The gate driving unit includes a plurality of any of the above gate driving circuits, and the plurality of gate driving circuits are arranged in cascade. An (n−4)th stage gate control signal output by an (n−4)th stage gate driving circuit serves as the pull-up control signal received by the pull-up control module of the n-th stage gate driving circuit. DESCRIPTION OF DRAWINGS FIG. 1 is a schematic block diagram f of a gate driving circuit provided by an embodiment of the present disclosure; FIG. 2 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure; FIG. 3 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present disclosure; FIG. 4 is a timing diagram of a corresponding gate driving circuit provided by an embodiment of the present disclosure; FIG. 5 is a simulation timing diagram before the improvement of a corresponding gate driving circuit provided by an embodiment of the present disclosure; FIG. 6 is a simulation timing diagram after the improvement of a corresponding gate driving circuit provided by an embodiment of the present disclosure; FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure; FIG. 8 is a cascade relationship diagram of a plurality of gate driving circuits provided by an embodiment of the present disclosure; FIG. 9 is a schematic diagram showing a corresponding relationship between gate driving circuits and high-frequenc