US-20260127997-A1 - DISPLAY DEVICE, DISPLAY DRIVING CHIP, AND DISPLAY DRIVING METHOD

US20260127997A1US 20260127997 A1US20260127997 A1US 20260127997A1US-20260127997-A1

Abstract

The disclosure provides a display device and a display driving chip and a display driving method thereof. The display panel includes a high refresh rate display area and a low refresh rate display area. The display driving chip generates a gate clock signal. The gate clock signal is utilized by the gate driver to generate first scan signals for driving the high refresh rate display area and second scan signals for driving the low refresh rate display area. Both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period. Only the high refresh rate display area is refreshed during a partial refresh frame period. The gate clock signal has different active periods or different swings in different parts of the full refresh frame period (corresponding to different refresh rate display areas).

Inventors

Tso-Hua Chien

Assignees

NOVATEK MICROELECTRONICS CORP.

Dates

Publication Date: 20260507
Application Date: 20251107

Claims (19)

1 . A display driving chip, comprising: a controller, configured to generate a gate clock signal to control a gate driver of a display panel, wherein a display area of the display panel comprises a high refresh rate display area and a low refresh rate display area, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period and only the high refresh rate display area is refreshed during a partial refresh frame period, wherein the gate clock signal is utilized by the gate driver to generate a plurality of first scan signals to drive a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals to drive a plurality of scan lines of the low refresh rate display area, and the gate clock signal has a first active period in a first part of the full refresh frame period, the first part of the full refresh frame period corresponds to the high refresh rate display area, the gate clock signal has a second active period greater than the first active period in a second part of the full refresh frame period, and the second part of the full refresh frame period corresponds to the low refresh rate display area.
2 . The display driving chip according to claim 1 , wherein the gate clock signal has a third active period same as the first active period in a first part of the partial refresh frame period, the first part of the partial refresh frame period corresponds to the high refresh rate display area, the gate clock signal stops switching in a second part of the partial refresh frame period, and the second part of the partial refresh frame period corresponds to the low refresh rate display area.
3 . The display driving chip according to claim 2 , wherein: the controller is configured to output a reset pulse and an additional reset pulse to the gate driver during the partial refresh frame period; and during the partial refresh frame period, the reset pulse occurs before a plurality of gate clock signals start toggling and the additional reset pulse occurs after the plurality of gate clock signals stop toggling.
4 . The display driving chip according to claim 2 , wherein in one refresh frame period composed of M full refresh frame periods and N partial refresh periods, where M and N are at least one, an average value of the active periods of the gate clock signal corresponding to the low refresh rate display area in the M full refresh frame periods and the active periods of the gate clock signal corresponding to the low refresh rate display area in the N partial refresh frame periods is close to or equals to an average value of the active periods of the gate clock signal corresponding to the high refresh rate display area in the M full refresh frame periods and the active periods of the gate clock signal corresponding to the high refresh rate display area in the N partial refresh frame periods.
5 . A display driving chip, comprising: a controller, configured to output a gate clock signal to control a gate driver of a display panel, wherein a display area of the display panel comprises a high refresh rate display area and a low refresh rate display area, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period and only the high refresh rate display area is refreshed during a partial refresh frame period, wherein the gate clock signal is utilized by the gate driver to generate a plurality of first scan signals to drive a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals to drive a plurality of scan lines of the low refresh rate display area, and the gate clock signal has a first swing in a first part of the full refresh frame period, the first part of the full refresh frame period corresponds to the high refresh rate display area, the gate clock signal has a second swing greater than the first swing in a second part of the full refresh frame period, and the second part of the full refresh frame period corresponds to the low refresh rate display area.
6 . The display driving chip according to claim 5 , wherein the gate clock signal has a third swing same as the first swing in a first part of the partial refresh frame period, the first part of the partial refresh frame period corresponds to the high refresh rate display area, the gate clock stays at an inactive voltage level in a second part of the partial refresh frame period, and the second part of the partial refresh frame period corresponds to the low refresh rate display area.
7 . The display driving chip according to claim 5 , wherein the gate clock signal switches between a low logic level and a high logic level, and during the full refresh frame period, the low logic level of the gate clock signal corresponding to the low refresh rate display area is lower than the low logic level of the gate clock signal corresponding the high refresh rate display area.
8 . The display driving chip according to claim 5 , wherein the gate clock signal switches between a low logic level and a high logic level, and during the full refresh frame period, the high logic level of the gate clock signal corresponding to the low refresh rate display area is higher than the high logic level of the gate clock signal corresponding to the high refresh rate display area.
9 . A display device, comprising: a display panel, comprising: an active display area, comprising a high refresh rate display area and a low refresh rate display area; and a gate driver, used to generate a plurality of first scan signals for driving a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals for driving a plurality of scan lines of the low refresh rate display area; and a display driving chip, comprising: a controller, configured to generate a gate clock signal to control the gate driver of the display panel, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period and only the high refresh rate display area is refreshed during a partial refresh frame period, wherein the gate clock signal is utilized by the gate driver to generate the plurality of first scan signals and the plurality of second scan signals, and the gate clock signal has a first active period in a first part of the full refresh frame period, the first part of the full refresh frame period corresponds to the high refresh rate display area, the gate clock signal has a second active period greater than the first active period in a second part of the full refresh frame period, and the second part of the full refresh frame period corresponds to the low refresh rate display area.
10 . The display device according to claim 9 , wherein the gate clock signal has a third active period same as the first active period in a first part of the partial refresh frame period, the first part of the partial refresh frame period corresponds to the high refresh rate display area, the gate clock signal stops switching in a second part of the partial refresh frame period, and the second part of the partial refresh frame period corresponds to the low refresh rate display area.
11 . The display device according to claim 10 , wherein the controller is configured to output a reset pulse and an additional reset pulse to the gate driver during the partial refresh frame period and during the partial refresh frame period, the reset pulse occurs before a plurality of gate clock signals start toggling and the additional reset pulse occurs after the plurality of gate clock signals stop toggling.
12 . The display device according to claim 10 , wherein in one refresh frame period composed of M full refresh frame periods and N partial refresh periods, where M and N are at least one, an average value of the active periods of the gate clock signal corresponding to the low refresh rate display area in the M full refresh frame periods and the active periods of the gate clock signal corresponding to the low refresh rate display area in the N partial refresh frame periods is close to or equals to an average value of the active periods of the gate clock signal corresponding to the high refresh rate display area in the M full refresh frame periods and the active periods of the gate clock signal corresponding to the high refresh rate display area in the N partial refresh frame periods.
13 . A display device, comprising: a display panel, comprising: an active display area, comprising a high refresh rate display area and a low refresh rate display area; and a gate driver, used to generate a plurality of first scan signals for driving a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals for driving a plurality of scan lines of the low refresh rate display area; and a display driving chip, comprising: a controller, configured to output a gate clock signal to control the gate driver of the display panel, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period and only the high refresh rate display area is refreshed during a partial refresh frame period, wherein the gate clock signal is utilized by the gate driver to generate the plurality of first scan signals and the plurality of second scan signals, and the gate clock signal has a first swing in a first part of the full refresh frame period, the first part of the full refresh frame period corresponds to the high refresh rate display area, the gate clock signal has a second swing greater than the first swing in a second part of the full refresh frame period, and the second part of the full refresh frame period corresponds to the low refresh rate display area.
14 . The display device according to claim 13 , wherein the gate clock signal has a third swing same as the first swing in a first part of the partial refresh frame period, the first part of the partial refresh frame period corresponds to the high refresh rate display area, the gate clock stays at an inactive voltage level in a second part of the partial refresh frame period, and the second part of the partial refresh frame period corresponds to the low refresh rate display area.
15 . The display device according to claim 13 , wherein the gate clock signal switches between a low logic level and a high logic level and during the full refresh frame period, the low logic level of the gate clock signal corresponding to the low refresh rate display area is lower than the low logic level of the gate clock signal corresponding the high refresh rate display area.
16 . The display device according to claim 13 , wherein the gate clock signal switches between a low logic level and a high logic level and during the full refresh frame period, the high logic level of the gate clock signal corresponding to the low refresh rate display area is higher than the high logic level of the gate clock signal corresponding to the high refresh rate display area.
17 . A display driving method, comprising: generating a gate clock signal to control a gate driver of a display panel, wherein a display area of the display panel comprises a high refresh rate display area and a low refresh rate display area, wherein both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period and only the high refresh rate display area is refreshed during a partial refresh frame period, wherein the gate clock signal is utilized by the gate driver to generate a plurality of first scan signals for driving a plurality of scan lines of the high refresh rate display area and a plurality of second scan signals for driving a plurality of scan lines of the low refresh rate display area, and the gate clock signal has different active periods in respective time periods of the full refresh frame period or the gate clock signal has different swings in respective time periods of the full refresh frame period.
18 . The display driving method according to claim 17 , wherein the gate clock signal has a first active period in a first part of the full refresh frame period, the first part of the full refresh frame period corresponds to the high refresh rate display area, the gate clock signal has a second active period greater than the first active period in a second part of the full refresh frame period, and the second part of the full refresh frame period corresponds to the low refresh rate display area.
19 . The display driving method according to claim 17 , wherein the gate clock signal has a first swing in a first part of the full refresh frame period, the first part of the full refresh frame period corresponds to the high refresh rate display area, the gate clock signal has a second swing greater than the first swing in a second part of the full refresh frame period, and the second part of the full refresh frame period corresponds to the low refresh rate display area.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of U.S. provisional application Ser. No. 63/717,793, filed on Nov. 7, 2024. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND Technical Field The disclosure relates to an electronic circuit, and more particularly to a display device and a display driving chip and a display driving method thereof. Description of Related Art On a traditional display panel, the entire display area of the display panel displays one or more images at the same refresh rate. In some applications, such as mobile applications, the entire display area of the display panel may be divided into multiple smaller display areas, but different areas all display the images at the same refresh rate. In many usage scenarios, only a certain display area often needs to be frequently refreshed (such as playing an animation), while another display area shows static image contents and does not need to be frequently refreshed. When the entire display area (all divided display areas) of the traditional display panel operates at a high refresh rate, the power consumption of the display panel is high. At this time, for display areas that do not need to be frequently refreshed, the high refresh rate is a waste of power. When the entire display area of the traditional display panel operates at a low refresh rate, although the power consumption of the display panel is low, the refresh rate is too low for the display area that need to be frequently refreshed. SUMMARY The disclosure provides a display device and a display driving chip and a display driving method thereof, so that different display areas (regions) in the same display panel adaptively have different refresh rates. In an embodiment of the disclosure, the display driving chip includes a controller. The controller is configured to generate a gate clock signal to control a gate driver of a display panel. A display area of the display panel includes a high refresh rate display area and a low refresh rate display area. Both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period and only the high refresh rate display area is refreshed during a partial refresh frame period. The gate clock signal is utilized by the gate driver to generate multiple first scan signals and multiple second scan signals. The first scan signals are used to drive multiple scan lines in the high refresh rate display area and the second scan signals are used to drive multiple scan lines in the low refresh rate display area. The gate clock signal has a first active period in a first part of the full refresh frame period (the first part of the full refresh frame period corresponds to the high refresh rate display area) and the gate clock signal has a second active period greater than the first active period in a second part of the full refresh frame period (the second part of the full refresh frame period corresponds to the low refresh rate display area). In an embodiment of the disclosure, the display driving chip includes a controller. The controller is configured to output a gate clock signal to control a gate driver of a display panel. A display area of the display panel includes a high refresh rate display area and a low refresh rate display area. Both the high refresh rate display area and the low refresh rate display area are refreshed during a full refresh frame period and only the high refresh rate display area is refreshed during a partial refresh frame period. The gate clock signal is utilized by the gate driver to generate multiple first scan signals and multiple second scan signals. The first scan signals are used to drive multiple scan lines in the high refresh rate display area and the second scan signals are used to drive multiple scan lines in the low refresh rate display area. The gate clock signal has a first swing in a first part of the full refresh frame period (the first part of the full refresh frame period corresponds to the high refresh rate display area) and the gate clock signal has a second swing greater than the first swing in a second part of the full refresh frame period (the second part of the full refresh frame period corresponds to the low refresh rate display area). In an embodiment of the disclosure, the display device includes a display panel and a display driving chip. The display panel includes an active display area and a gate driver. The active display area includes a high refresh rate display area and a low refresh rate display area. The gate driver is used to generate multiple first scan signals for driving multiple scan lines in the high refresh rate display area and multiple second scan signals for driving multiple scan lines in the low refresh rate display area. The display driving chip includes a controller. The controller is configured t