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US-20260128003-A1 - DISPLAY PANEL AND DISPLAY DEVICE

US20260128003A1US 20260128003 A1US20260128003 A1US 20260128003A1US-20260128003-A1

Abstract

A display panel includes a driver circuit which includes n stages of cascaded shift register units; the first output terminal or the second output terminal of an x th -stage shift register unit is electrically connected to the forward input terminal of a y th -stage shift register unit, and the reverse input terminal of the y th -stage shift register unit is electrically connected to the first output terminal or the second output terminal of a k th -stage shift register unit; in a forward scan mode, a first-stage shift register unit to an n th -stage shift register unit sequentially output the effective pulse of a first gate signal and sequentially output the effective pulse of a second gate signal; in a reverse scan mode, the n th -stage shift register unit to the first-stage shift register unit sequentially output the effective pulse of the first gate signal and sequentially output the effective pulse of the second gate signal.

Inventors

  • Mengmeng ZHANG

Assignees

  • Wuhan Tianma Microelectronics Co., Ltd. Shanghai Branch

Dates

Publication Date
20260507
Application Date
20251218
Priority Date
20250626

Claims (20)

  1. 1 . A display panel, comprising a driver circuit, wherein the driver circuit comprises n stages of cascaded shift register units, wherein n is a positive integer greater than or equal to 2; a shift register unit among the n stages of cascaded shift register units comprises a scan control module, a drive control module, a first output module, a second output module, a forward input terminal, a reverse input terminal, a forward control terminal, a reverse control terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first output terminal and a second output terminal; in a same shift register unit among the n stages of cascaded shift register units, the scan control module is electrically connected to the forward input terminal, the reverse input terminal, the forward control terminal, the reverse control terminal and an input node, the drive control module is at least electrically connected to the input node, the first clock terminal, a first node and a second node, the first output module is at least electrically connected to the first node, the second node, the second clock terminal and the first output terminal, and the second output module is at least electrically connected to the first node, the second node, the third clock terminal and the second output terminal; the first output terminal or the second output terminal of an x th -stage shift register unit is electrically connected to the forward input terminal of a y th -stage shift register unit, and the reverse input terminal of the y th -stage shift register unit is electrically connected to the first output terminal or the second output terminal of a k th -stage shift register unit; wherein 1≤x<y<k≤n, and x, y and k are positive integers; in the same shift register unit, an effective pulse of a first gate signal output from the first output terminal and an effective pulse of a second gate signal output from the second output terminal are sequentially shifted; an operating mode of the display panel comprises a forward scan mode and a reverse scan mode; in the forward scan mode, a first-stage shift register unit to an n th -stage shift register unit sequentially output the effective pulse of the first gate signal and sequentially output the effective pulse of the second gate signal; in the reverse scan mode, the n th -stage shift register unit to the first-stage shift register unit sequentially output the effective pulse of the first gate signal and sequentially output the effective pulse of the second gate signal.
  2. 2 . The display panel according to claim 1 , wherein the forward control terminal is configured to receive a forward scan control signal, and the reverse control terminal is configured to receive a reverse scan control signal; in the forward scan mode, the forward scan control signal is at an effective level, and the reverse scan control signal is at an ineffective level; in the reverse scan mode, the reverse scan control signal is at an effective level, and the forward scan control signal is at an ineffective level.
  3. 3 . The display panel according to claim 1 , wherein the scan control module comprises a forward scan control transistor and a reverse scan control transistor; a gate of the forward scan control transistor is electrically connected to the forward control terminal, a first electrode of the forward scan control transistor is electrically connected to the forward input terminal, and a second electrode of the forward scan control transistor is electrically connected to the input node; a gate of the reverse scan control transistor is electrically connected to the reverse control terminal, a first electrode of the reverse scan control transistor is electrically connected to the reverse input terminal, and a second electrode of the reverse scan control transistor is electrically connected to the input node.
  4. 4 . The display panel according to claim 1 , wherein a display duration of one frame of the display panel comprises a plurality of clock cycles; within one clock cycle of the plurality of clock cycles, in the same shift register unit, an effective pulse of a second clock signal of the second clock terminal and an effective pulse of a third clock signal of the third clock terminal are sequentially shifted.
  5. 5 . The display panel according to claim 4 , wherein when a duration of a clock cycle among the plurality of clock cycles is 2*T, the clock cycle comprises a first time period and a second time period which are consecutive and each have a duration of T; within the one clock cycle, in the same shift register unit, the effective pulse of the second clock signal and the effective pulse of the third clock signal are both within the first time period or the second time period.
  6. 6 . The display panel according to claim 4 , wherein within the one clock cycle, in the same shift register unit, a duration of an effective pulse of a first clock signal is before a duration of the effective pulse of the second clock signal.
  7. 7 . The display panel according to claim 6 , wherein when a duration of a clock cycle among the plurality of clock cycles is 2*T, the clock cycle comprises a first time period and a second time period which are consecutive and each have a duration of T; within the one clock cycle, in the same shift register unit, the effective pulse of the first clock signal is within the first time period, and the effective pulse of the second clock signal and the effective pulse of the third clock signal are within the second time period.
  8. 8 . The display panel according to claim 6 , wherein when a duration of a clock cycle among the plurality of clock cycles is 2*T, the clock cycle comprises a first time period and a second time period which are consecutive and each have a duration of T; within the one clock cycle, in the same shift register unit, the effective pulse of the first clock signal and the effective pulse of the second clock signal are within the first time period, and the effective pulse of the third clock signal is within the second time period.
  9. 9 . The display panel according to claim 4 , wherein within the one clock cycle in the forward scan mode, a duration of the effective pulse of the third clock signal in the x th -stage shift register unit is before a duration of the effective pulse of the second clock signal in the y th -stage shift register unit; within the one clock cycle in the reverse scan mode, the duration of the effective pulse of the third clock signal in the k th -stage shift register unit is before the duration of the effective pulse of the second clock signal in the y th -stage shift register unit.
  10. 10 . The display panel according to claim 1 , wherein in the forward scan mode, a duration of the effective pulse of the second gate signal output by an i th -stage shift register unit is before a duration of the effective pulse of the first gate signal output by an (i+1) th -stage shift register unit; in the reverse scan mode, the duration of the effective pulse of the second gate signal output by the (i+1) th -stage shift register unit is before the duration of the effective pulse of the first gate signal output by the i th -stage shift register unit.
  11. 11 . The display panel according to claim 1 , wherein in the forward scan mode, the duration of the effective pulse of the first gate signal output by the i th -stage shift register unit is before the duration of the effective pulse of the first gate signal output by the (i+1) th -stage shift register unit; the duration of the effective pulse of the second gate signal output by the i th -stage shift register unit overlaps with the duration of the effective pulse of the first gate signal output by the (i+1) th -stage shift register unit; wherein i is a positive integer less than or equal to n; in the reverse scan mode, the duration of the effective pulse of the first gate signal output by the (i+1) th -stage shift register unit is before the duration of the effective pulse of the first gate signal output by the i th -stage shift register unit; the duration of the effective pulse of the second gate signal output by the (i+1) th -stage shift register unit overlaps with the duration of the effective pulse of the first gate signal output by the i th -stage shift register unit.
  12. 12 . The display panel according to claim 1 , further comprising 2*m first clock signal lines and 2*m second clock signal lines when x=y−m and k=y+m, wherein m is a positive integer; a display duration of one frame of the display panel comprises a plurality of clock cycles; a duration of a clock cycle among the plurality of clock cycles is greater than or equal to 2*m*H, wherein H is a clock unit duration; within one of the plurality of clock cycles, effective pulses of clock signals transmitted by the first clock signal lines are sequentially shifted; and within the one clock cycle, effective pulses of clock signals transmitted by the second clock signal lines are sequentially shifted; 2*m adjacent stages of shift register units among the n stages of cascaded shift register units constitute a shift register unit group; in a same shift register unit group, the first clock terminal of a stage of shift register unit among the 2*m adjacent stages of shift register units is electrically connected to a corresponding one of the first clock signal lines, and the third clock terminal of the stage of shift register unit is electrically connected to a corresponding one of the second clock signal lines; the second clock terminal of an (i+m) th -stage shift register unit and the first clock terminal of an i th -stage shift register unit are electrically connected to a same first clock signal line among the first clock signal lines, wherein i is a positive integer less than or equal to n.
  13. 13 . The display panel according to claim 12 , wherein when m is greater than 1, a third clock signal of the i th -stage shift register unit is same as a first clock signal of an (i+m+1) th -stage shift register unit.
  14. 14 . The display panel according to claim 1 , further comprising 2*m first clock signal lines and 2*m second clock signal lines when x=y−m and k=y+m; a display duration of one frame of the display panel comprises a plurality of clock cycles; a duration of a clock cycle among the plurality of clock cycles is greater than or equal to 2*m*H, wherein H is a clock unit duration; within one of the plurality of clock cycles, effective pulses of clock signals transmitted by the first clock signal lines are sequentially shifted; and within the one clock cycle, effective pulses of clock signals transmitted by the second clock signal lines are sequentially shifted; 2*m adjacent stages of shift register units among the n stages of cascaded shift register units constitute a shift register unit group; in a same shift register unit group, the first clock terminal of a stage of shift register unit among the 2*m adjacent stages of shift register units is electrically connected to a corresponding one of the first clock signal lines, and the second clock terminal of the stage of shift register unit is electrically connected to a corresponding one of the second clock signal lines; the third clock terminal of an (i+m) th -stage shift register unit and the first clock terminal of an i th -stage shift register unit are electrically connected to a same first clock signal line among the first clock signal lines, wherein i is a positive integer less than or equal to n.
  15. 15 . The display panel according to claim 14 , wherein when m is greater than 1, a second clock signal of the i th -stage shift register unit is same as a first clock signal of an (i+m−1) th -stage shift register unit.
  16. 16 . The display panel according to claim 1 , further comprising m first start signal lines and m second start signal lines when x=y−m and k=y+m, wherein m is a positive integer; the forward input terminal of a stage of the shift register unit among the first-stage shift register unit to an m th -stage shift register unit is electrically connected to a corresponding one of the first start signal lines; the reverse input terminal of a stage of the shift register unit among an (n−m+1) th -stage shift register unit to the n th -stage shift register unit is electrically connected to a corresponding one of the second start signal lines; in the forward scan mode, the first start signal lines sequentially transmit an effective pulse of a first start signal; in the reverse scan mode, the second start signal lines sequentially transmit an effective pulse of a second start signal.
  17. 17 . The display panel according to claim 1 , further comprising a display region; wherein the display region is provided with a plurality of pixel circuits arranged in an array; a pixel circuit among the plurality of pixel circuits at least comprises a first preset module and a second preset module; the first gate signal and the second gate signal of the same shift register unit are configured to control first preset module and the second preset module of a same pixel circuit among the plurality of pixel circuits to be turned on or turned off, respectively; wherein the pixel circuit comprises a compensation module, a data write module, a reset module and a drive module; the drive module comprises a drive transistor; the data write module is electrically connected to a first electrode of the drive transistor; the compensation module is electrically connected between a second electrode of the drive transistor and a gate of the drive transistor; the reset module is electrically connected to the gate of the drive transistor; the first preset module comprises the reset module; the second preset module comprises at least one of the data write module or the compensation module.
  18. 18 . The display panel according to claim 1 , wherein the drive control module comprises a first node control sub-module, a second node control sub-module and a node mutual control sub-module; the shift register unit further comprises a fourth clock terminal, a first level terminal and a second level terminal; in the same shift register unit, the first node control sub-module is electrically connected to the input node, the first clock terminal and the first node; the second node control sub-module is electrically connected to the first clock terminal, the first level terminal and the second node; the node mutual control sub-module is electrically connected to the second level terminal, the first node, the second node, the first clock terminal and the fourth clock terminal; wherein a duration of an effective pulse of a fourth clock signal received by the fourth clock terminal does not overlap with a duration of an effective pulse of a first clock signal received by the first clock terminal.
  19. 19 . The display panel according to claim 18 , wherein the second clock terminal is configured to receive a second clock signal, and the third clock terminal is configured to receive a third clock signal; the fourth clock signal is same as the second clock signal or the third clock signal.
  20. 20 . The display panel according to claim 1 , wherein the shift register unit further comprises a first voltage regulation module; and in the same shift register unit, at least one of the first output module or the second output module is electrically connected to the first node through the first voltage regulation module; or the shift register unit further comprises a second voltage regulation module and a third voltage regulation module; in the same shift register unit, the first output module is electrically connected to the first node through the second voltage regulation module; and the second output module is electrically connected to the first node through the third voltage regulation module.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to Chinese Patent Application No. 202510876077.3, filed on Jun. 26, 2025, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the field of display technology and, in particular, to a display panel and a display device. BACKGROUND With the advancement of display technology, electronic products featuring display functions have been widely adopted across various domains. The electronic products with display capabilities, such as televisions, mobile phones, computers and personal digital assistants, have become indispensable components in people's daily lives and work. The display panel serves as the core structure enabling the display function within electronic products. A display panel typically includes multiple pixel circuits arranged in an array and a driver circuit. The driver circuit can perform progressive scanning on the pixel circuits by supplying gate drive signals to each row of pixels to enable the pixel circuits in each row to display and emit light, thereby allowing the display panel to present corresponding images. However, due to the limitation of the functions and structures of the driver circuits, when a pixel circuit includes multiple functional modules, different driver circuits need to be set to separately supply gate drive signals to different functional modules in the pixel circuit, and as a result, the driver circuits occupy a significant amount of space, which is unfavorable for achieving the narrow-bezel design of the display panel, thereby adversely affecting the display performance of the display panel. SUMMARY The present disclosure provides a display panel and a display device to reduce the size of the driver circuit, thereby facilitating the implementation of the narrow-bezel design of the display panel and improving the display performance of the display panel. In a first aspect, embodiments of the present disclosure provide a display panel. The display panel includes a driver circuit. The driver circuit includes n stages of cascaded shift register units, where n is a positive integer greater than or equal to 2. The shift register unit includes a scan control module, a drive control module, a first output module, a second output module, a forward input terminal, a reverse input terminal, a forward control terminal, a reverse control terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first output terminal and a second output terminal. In the same shift register unit, the scan control module is electrically connected to the forward input terminal, the reverse input terminal, the forward control terminal, the reverse control terminal and an input node, the drive control module is at least electrically connected to the input node, the first clock terminal, a first node and a second node, the first output module is at least electrically connected to the first node, the second node, the second clock terminal and the first output terminal, and the second output module is at least electrically connected to the first node, the second node, the third clock terminal and the second output terminal. The first output terminal or the second output terminal of an xth-stage shift register unit is electrically connected to the forward input terminal of a yth-stage shift register unit, and the reverse input terminal of the yth-stage shift register unit is electrically connected to the first output terminal or the second output terminal of a kth-stage shift register unit, where 1≤x<y<k≤n, and x, y and k are positive integers. In the same shift register unit, the effective pulse of a first gate signal output from the first output terminal and the effective pulse of a second gate signal output from the second output terminal are sequentially shifted. The operating mode of the display panel includes a forward scan mode and a reverse scan mode. In the forward scan mode, a first-stage shift register unit to an nth-stage shift register unit sequentially output the effective pulse of the first gate signal and sequentially output the effective pulse of the second gate signal. In the reverse scan mode, the nth-stage shift register unit to the first-stage shift register unit sequentially output the effective pulse of the first gate signal and sequentially output the effective pulse of the second gate signal. In a second aspect, the present disclosure provides a display device. The display panel includes the display panel described in the first aspect. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a structure diagram of a display panel in the related art; FIG. 2 is a structure diagram of another display panel in the related art; FIG. 3 is a structure diagram of a display panel according to an embodiment of the present disclosure; FIG. 4 is a structure diagram of a shift register unit according to an embodiment of the present disclosure;