US-20260128005-A1 - PIXEL AND DISPLAY DEVICE INCLUDING THE SAME
Abstract
A pixel is disclosed that includes a first transistor, a second transistor, a third transistor, a light emitting diode, a first capacitor, and a second capacitor. The first transistor includes a first gate electrode connected to a first node, a second gate electrode which receives a write gate signal or an emission control signal, a first electrode which receives a first power voltage, and a second electrode connected to a second node.
Inventors
- Keunwoo Kim
Assignees
- SAMSUNG DISPLAY CO., LTD.
Dates
- Publication Date
- 20260507
- Application Date
- 20251230
- Priority Date
- 20230307
Claims (6)
- 1 . A pixel, comprising: a first transistor which includes a first gate electrode connected to a first node, a second gate electrode which receives an emission control signal, a first electrode which receives a first power voltage, and a second electrode connected to a second node; a second transistor which includes a gate electrode which receives a write gate signal, a first electrode connected to the first node, and a second electrode connected to a third node; a third transistor which includes a gate electrode which receives a compensation gate signal, a first electrode connected to the third node, and a second electrode connected to the second node; a light emitting diode which includes a first electrode connected to the second node and a second electrode which receives a second power voltage; a first capacitor which includes a first electrode connected to the third node and a second electrode which receives a data voltage; and a second capacitor which includes a first electrode connected to the first node and a second electrode which receives a third power voltage.
- 2 . The pixel of claim 1 , wherein a frame period includes: an initialization period in which the first gate electrode of the first transistor and the first electrode of the light emitting diode are initialized; a compensation period in which a threshold voltage of the first transistor is compensated; a programming period in which the data voltage is written to the first gate electrode of the first transistor; and an emission period in which the light emitting diode emits a light.
- 3 . The pixel of claim 2 , wherein the write gate signal transitions from a turn-off voltage level to a turn-on voltage level in the initialization period, has the turn-on voltage level in the compensation period and the programming period, and has the turn-off voltage level in the emission period.
- 4 . The pixel of claim 2 , wherein the emission control signal transitions from a turn-off voltage level to a turn-on voltage level in the initialization period, has the turn-off voltage level in the programming period, and has the turn-on voltage level in the emission period.
- 5 . The pixel of claim 2 , wherein the first power voltage has a low voltage level in the initialization period, and has a high voltage level in the compensation period and the emission period.
- 6 . The pixel of claim 2 , wherein the second power voltage has a high voltage level in the initialization period and the compensation period, and has a low voltage level in the emission period.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional application of U.S. Patent Application No. 18/505,137, filed on November 9, 2023, which claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0029972 filed on March 07, 2023 in the Korean Intellectual Property Office (KIPO), the entire disclosures of which are incorporated by reference herein. BACKGROUND 1. Field Embodiments relate to a display device. More particularly, embodiments related to a pixel having a small area and a high-resolution display device including the pixel. 2. Description of the Related Art Methods of driving display devices may be classified as a simultaneous pixel-emission method and a sequential pixel-emission method. In the simultaneous emission method, all pixels may simultaneously emit light after data writing is sequentially completed on a row-by-row basis. In the sequential emission method, pixels may sequentially emit light on a row-by-row basis. Recently, demand for high-resolution display devices has increased. In order to implement a high-resolution display device, an area of a pixel may be reduced. SUMMARY Embodiments may provide a pixel having a small area and an increased luminance. Embodiments may provide a display device having an improved display quality by including the pixel. A pixel according to embodiments may include a first transistor which includes a first gate electrode connected to a first node, a second gate electrode which receives a write gate signal, a first electrode which receives a first power voltage, and a second electrode connected to a second node, a second transistor which includes a gate electrode which receives the write gate signal, a first electrode connected to the first node, and a second electrode connected to a third node, a third transistor which includes a gate electrode which receives a compensation gate signal, a first electrode connected to the third node, and a second electrode connected to the second node, a light emitting diode which includes a first electrode connected to the second node and a second electrode which receives a second power voltage, a first capacitor which includes a first electrode connected to the third node and a second electrode which receives a data voltage, and a second capacitor which includes a first electrode connected to the first node and a second electrode which receives a third power voltage. In an embodiment, a frame period may include an initialization period in which the first gate electrode of the first transistor and the first electrode of the light emitting diode are initialized, a compensation period in which a threshold voltage of the first transistor is compensated, a programming period in which the data voltage is written to the first gate electrode of the first transistor, and an emission period in which the light emitting diode emits a light. In an embodiment, the write gate signal may transition from a turn-off voltage level to a turn-on voltage level in the initialization period, may have the turn-on voltage level in the compensation period and the emission period, and may have an intermediate voltage level between the turn-off voltage level and the turn-on voltage level in the programming period. In an embodiment, the first power voltage may have a low voltage level in the initialization period, and may have a high voltage level in the compensation period and the emission period. In an embodiment, the second power voltage may have a high voltage level in the initialization period and the compensation period, and may have a low voltage level in the emission period. In an embodiment, the third power voltage may have a low voltage level in the initialization period, and may have a high voltage level in the compensation period, the programming period, and the emission period. In an embodiment, the compensation gate signal may have a turn-on voltage level in the initialization period and the compensation period, and may have a turn-off voltage level in the programming period and the emission period. A pixel according to embodiments may include a first transistor which includes a first gate electrode connected to a first node, a second gate electrode which receives an emission control signal, a first electrode which receives a first power voltage, and a second electrode connected to a second node, a second transistor which includes a gate electrode which receives a write gate signal, a first electrode connected to the first node, and a second electrode connected to a third node, a third transistor which includes a gate electrode which receives a compensation gate signal, a first electrode connected to the third node, and a second electrode connected to the second node, a light emitting diode which includes a first electrode connected to the second node and a second electrode which receives a second power voltage, a first capacitor which includes a first electrode connected to the third node and a seco