US-20260128012-A1 - DISPLAY SUBSTRATE CONFIGURED WITH DIFFERENT DRIVE MODES, DRIVING METHOD THEREOF, AND DISPLAY APPARATUS

US20260128012A1US 20260128012 A1US20260128012 A1US 20260128012A1US-20260128012-A1

Abstract

Provided is a display substrate, a drive method thereof and a display apparatus, the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, the pixel circuits include a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the first initial signal is an AC signal.

Inventors

Guangliang Shang
Jiangnan Lu
Li Wang
Mengyang WEN
Xing Yao
Libin Liu

Assignees

BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20260107

Claims (20)

1 . A display substrate, wherein drive modes for the display substrate comprise: a first drive mode and a second drive mode, wherein a refresh rate of the display substrate in the first drive mode is less than a refresh rate of the display substrate in the second drive mode, wherein the display substrate is configured to display a plurality of display frames, wherein in the first drive mode, the display frames comprise: a refresh frame and at least one maintain frame; wherein the display substrate comprises pixel circuits arranged in an array, the pixel circuits comprise a first initial signal line, a second initial signal line and a third initial signal line; wherein the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the second initial signal line provides a second initial signal in the refresh frame and the maintain frame, and an voltage value of a third initial signal provided by the third initial signal line is different from an voltage value of the first initial signal provided by the first initial signal line.
2 . The display substrate according to claim 1 , wherein the first initial signal comprises a first sub-initial signal and a second sub-initial signal, the first initial signal line provides the first sub-initial signal in the refresh frame and provides the second sub-initial signal in the maintain frame, and an average voltage value of the second sub-initial signal is greater than an average voltage value of the first sub-initial signal.
3 . The display substrate according to claim 1 , wherein the pixel circuits further comprise a data signal line, the data signal line provides a first data signal in the maintain frame, and a voltage value of the first data signal is constant, wherein the data signal line provides a second data signal during a partial time period of the refresh frame; and the voltage value of the first data signal is greater than or equal to a voltage value of the second data signal.
4 . The display substrate according to claim 1 , wherein the third initial signal line provides the third initial signal in the refresh frame and the maintain frame, the third initial signal is a Direct Current (DC) signal, and the voltage value of the third initial signal is constant.
5 . The display substrate according to claim 1 , wherein the third initial signal provided by the third initial signal line is an Alternating Current (AC) signal, the first initial signal provided by the first initial signal line is an AC signal, and a change period of the third initial signal is consistent with a change period of the first initial signal.
6 . The display substrate according to claim 1 , wherein the voltage value of the third initial signal provided by the third initial signal line is approximately a voltage value of a signal of a first power supply line.
7 . The display substrate according to claim 1 , wherein the second initial signal is a Direct Current (DC) signal, and a voltage value of the second initial signal is constant.
8 . The display substrate according to claim 1 , wherein the pixel circuits further comprise a write transistor, an anode reset transistor and a data signal line extending in a first direction, wherein the first initial signal line extends in a second direction, the data signal line is electrically connected to a first electrode of the write transistor, and the first initial signal line is electrically connected to a first electrode of the anode reset transistor.
9 . The display substrate according to claim 8 , wherein the pixel circuits further comprise a drive transistor, and the third initial signal line is electrically connected to a first electrode of the drive transistor.
10 . The display substrate according to claim 1 , wherein the pixel circuits further comprise: a reset signal line, a first scan signal line and a light emitting signal line; the refresh frame comprises an initialization stage, a data write stage and a refresh light emitting stage, the refresh light emitting stage comprises a plurality of first stages and a plurality of second stages, the first stage and the second stage are alternate, and the first first stage is before the first second stage; a signal of the reset signal line is a valid level signal in the initialization stage and an invalid level signal in the data write stage and the first stage; a signal of the first scan signal line is a valid level signal in the data write stage and an invalid level signal in the initialization stage and the first stage; a light emitting signal line is an invalid level signal in the initialization stage, the data write stage and the second stage, and is a valid level signal in the first stage; and the valid level signal is a level signal that causes a transistor to be turned on, the invalid level signal is a level signal that causes the transistor to be turned off, a duration of the first stage is equal to a duration of the light emitting signal line being a valid level signal, and a duration of the second stage is equal to a duration of the signal of the light emitting signal line being an invalid level signal.
11 . The display substrate according to claim 10 , wherein: the maintain frame comprises: a plurality of third stages and a plurality of fourth stages, the third stage and the fourth stage are alternate, a signal of the light emitting signal line in a last stage of the refresh light emitting stage and a signal in the first stage of the maintain frame are mutually inverse signals; a signal of the light emitting signal line is an invalid level signal in the third stage and is a valid level signal in the fourth stage; the first scan signal line and the reset signal line provide low-level signals in the fourth stage; and a duration of the third stage is equal to a duration of the signal of the light emitting signal line being an invalid level signal, and a duration of the fourth stage is equal to a duration of the signal of the light emitting signal line being a valid level signal.
12 . The display substrate according to claim 11 , wherein a first third stage comprises a first maintain sub-stage and a second maintain sub-stage, wherein the first maintain sub-stage is before the second maintain sub-stage, and a sum of durations of the first maintain sub-stage and the second maintain sub-stage is less than the duration of the signal of the light emitting signal line being an invalid level signal; the signal of the reset signal line is a valid level signal in the first maintain sub-stage and an invalid level signal in a first time period, wherein the first time period is a time period except the first maintain sub-stage in the first third stage; and the signal of the first scan signal line is a valid level signal in the second maintain sub-stage and an invalid level signal in a second time period, wherein the second time period is a time period except the second maintain sub-stage in the first third stage.
13 . The display substrate according to claim 12 , wherein the pixel circuits further comprise a second scan signal line; a signal of the second scan signal line is a valid level signal at the initialization stage and the data write stage, and is an invalid level signal at the first stage and the second stage; the signal of the second scan signal line is an invalid level signal in the third stage and the fourth stage; and a duration of the signal of the second scan signal line being a valid level signal is smaller than a duration of the signal of the light emitting signal line being an invalid level signal.
14 . The display substrate according to claim 12 , wherein the signals of the reset signal line and the first scan signal line are invalid level signals at the second stage.
15 . The display substrate according to claim 12 , wherein the signals of the reset signal line and the first scan signal line are invalid level signals from a second third stage to a Nth third stage, N is greater than or equal to 2, N=M/K, where M is a reference frequency of the display substrate, K is the refresh rate of the display substrate in the first drive mode, and the reference frequency is the refresh rate of the display substrate in the second drive mode or a preset refresh rate.
16 . The display substrate according to claim 12 , wherein the second stage comprises a first refresh sub-stage; the signal of the first scan signal line is an invalid level signal in the second stage; and the signal of the reset signal line is a valid level signal in the first refresh sub-stage and an invalid level signal in a third time period, wherein the third time period is a time period except the first refresh sub-stage in the second stage.
17 . The display substrate according to claim 16 , wherein any third stage from a second third stage to a Nth third stage comprises a third maintain sub-stage; the signal of the first scan signal line is an invalid level signal from the second third stage to the Nth third stage; and the signal of the reset signal line is a valid level signal at the third maintain sub-stage in any third stage from the second third stage to the Nth third stage, and is an invalid level signal in a fourth time period, the fourth time period is a time period except the third maintain sub-stage in any third stage from the second third stage to the Nth third stage.
18 . The display substrate according to claim 17 , wherein a frequency at which the signal of the reset signal line is a valid level signal is equal to a frequency at which the signal of the light emitting signal line is an invalid level signal.
19 . The display substrate according to claim 12 , wherein the second stage comprises a second refresh sub-stage; the signal of the reset signal line is an invalid level signal in the second stage; and the signal of the first scan signal line is a valid level signal in the second refresh sub-stage and an invalid level signal in a fifth time period, wherein the fifth time period is a time period except the second refresh sub-stage in the second stage.
20 . A display apparatus, comprising: a display substrate, wherein drive modes for the display substrate comprise: a first drive mode and a second drive mode, wherein a refresh rate of the display substrate in the first drive mode is less than a refresh rate of the display substrate in the second drive mode, wherein the display substrate is configured to display a plurality of display frames, wherein in the first drive mode, the display frames comprise: a refresh frame and at least one maintain frame; wherein the display substrate comprises pixel circuits arranged in an array, the pixel circuits comprise a first initial signal line, a second initial signal line and a third initial signal line; wherein the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the second initial signal line provides a second initial signal in the refresh frame and the maintain frame, and an voltage value of a third initial signal provided by the third initial signal line is different from an voltage value of the first initial signal provided by the first initial signal line.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) The present application is a continuation of U.S. patent application Ser. No. 19/032,469 filed on Jan. 21, 2025, which is a continuation of U.S. application Ser. No. 18/027,376 filed on Mar. 21, 2023, which is a U.S. National Phase Entry of International Application No. PCT/CN2022/092379 having an international filing date of May 12, 2022. The entire contents of the above-identified applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to, but is not limited to, the field of display technology, and particularly relates to a display substrate and a drive method thereof, and a display apparatus. BACKGROUND An Organic Light Emitting Diode (OLED for short) and a Quantum-dot Light Emitting Diode (QLED for short) are active light emitting display apparatuses and have advantages such as self-light emitting, wide viewing angle, high contrast ratio, low power consumption, very high response speed, lightness and thinness, flexibility, and low costs. With the continuous development of display technologies, flexible displays that use OLEDs or QLEDs as light emitting elements and control signals by thin film transistors (TFTs) have become mainstream products in the field of display at present. SUMMARY The following is a summary of subject matters described herein in detail. The summary is not intended to limit the protection scope of claims. In a first aspect, the present disclosure provides a display substrate, drive modes of the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, wherein in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, wherein the pixel circuit includes a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, wherein the first initial signal is an AC signal. In some possible implementations, the data signal line provides a second data signal during a partial time period of the refresh frame; the voltage value of the first data signal is greater than or equal to the voltage value of the second data signal. In some possible implementations, the first initial signal includes: a first sub-initial signal and a second sub-initial signal; the first initial signal line provides the first sub-initial signal in the refresh frame and provides the second sub-initial signal in the maintain frame; an average voltage value of the second sub-initial signal is greater than an average voltage value of the first sub-initial signal. In some possible implementations, the pixel circuit further includes: a second initial signal line; the second initial signal line provides a second initial signal to the second reset transistor in the refresh frame and the maintain frame, wherein the second initial signal is a DC signal and the voltage value of the second initial signal is constant. In some possible implementations, the pixel circuit further includes: a reset signal line, a first scan signal line and a light emitting signal line; the refresh frame includes an initialization stage, a data write stage and a refresh light emitting stage; the refresh light emitting stage includes a plurality of first stages and a plurality of second stages, the first stage and the second stage are alternate, and the first first stage is before the first second stage; the signal of the reset signal line is a valid level signal in the initialization stage and an invalid level signal in the data write stage and the first stage; the signal of the first scan signal line is a valid level signal in the data write stage and an invalid level signal in the initialization stage and the first stage; the light emitting signal line is an invalid level signal in the initialization stage, the data write stage and the second stage, and is a valid level signal in the first stage; wherein, the valid level signal is a level signal that causes the transistor to be turned on, the invalid level signal is a level signal that causes the transistor to be turned off, the duration of the first stage is equal to the duration of the light emitting signal line being a valid level signal, and the duration of the second stage is equal to the duration of the signal of the light emitting signal line being an invalid level signal. In some possible implementations, the maintain frame includes: a plurality of third stages and a plurality of fourth stages, the third stage and the fourth stage are alternate, the signal of the light emitting signal line in