US-20260128014-A1 - DISPLAY DEVICE

US20260128014A1US 20260128014 A1US20260128014 A1US 20260128014A1US-20260128014-A1

Abstract

A display device includes: a substrate comprising a display area in which images are displayed and a non-display area different from the display area; and a gate driving panel circuit disposed in the non-display area, and comprising an output buffer block that comprises a carry output buffer configured to output a carry signal based on a carry clock signal, a scan output buffer configured to output a scan signal based on a scan clock signal, and a sensing output buffer configured to output a sensing signal based on a sensing clock signal. Among the carry output buffer, the scan output buffer, and the sensing output buffer, the carry output buffer may be located furthest away from the display area or located closest to an edge of the substrate.

Inventors

Jaeyi CHOI
SooHong Choi
HongJae Shin

Assignees

LG DISPLAY CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251230
Priority Date: 20230228

Claims (20)

1 . A display device, comprising: a substrate comprising a display area in which images are displayed and a non-display area different from the display area; and a gate driving panel circuit disposed in the non-display area, and comprising an output buffer block that comprises a carry output buffer configured to output a carry signal based on a carry clock signal, a scan output buffer configured to output a scan signal based on a scan clock signal, and a sensing output buffer configured to output a sensing signal based on a sensing clock signal, wherein among the carry output buffer, the scan output buffer, and the sensing output buffer, the carry output buffer is located furthest away from the display area or located closest to an edge of the substrate.
2 . The display device of claim 1 , further comprising: a clock signal line area in which a plurality of clock signal lines are disposed, wherein the plurality of clock signal lines comprise at least one of: at least one carry clock signal line for delivering the carry clock signal; at least one scan clock signal line for delivering the scan clock signal; and at least one sensing clock signal line for delivering the sensing clock signal.
3 . The display device of claim 2 , wherein among the carry clock signal line, the scan clock signal line, and the sensing clock signal line, the carry clock signal line is located furthest away from the display area or located closest to the edge of the substrate.
4 . The display device of claim 2 , wherein the scan clock signal line and the carry clock signal line are located further outwardly than the gate driving panel circuit.
5 . The display device of claim 2 , wherein a width of the scan clock signal line is greater than a width of the carry clock signal line.
6 . The display device of claim 2 , wherein a width of the sensing clock signal line is greater than a width of the carry clock signal line.
7 . The display device of claim 2 , wherein a width of the scan clock signal line is substantially equal to a width of the sensing clock signal line.
8 . The display device of claim 2 , wherein a number of carry clock signal lines, a number of scan clock signal lines, and a number of sensing clock signal lines, which are disposed in a portion of the non-display area, are equal to each other.
9 . The display device of claim 1 , further comprising: a first power line area disposed between a clock signal line area in which a plurality of clock signal lines are disposed and the display area, wherein the first power line area comprises at least one of: at least one gate high voltage line for delivering at least one type of gate high voltage; a start signal line for delivering a start signal; a driving sequence control signal line for delivering at least one of a first type of driving control signal and a second type of driving control signal; a reset signal line for delivering a reset signal; and a line selection signal line for delivering a line selection signal.
10 . The display device of claim 9 , further comprising: a second power line area disposed between the first power line area and the display area, wherein the second power line area comprises at least one gate low voltage line for delivering at least one type of gate low voltage.
11 . The display device of claim 10 , further comprising: an overcoat layer disposed over the substrate and extending from the display area to the non-display area, wherein the overcoat layer comprises at least one of: a first trench located between a gate driving panel circuit area where the gate driving panel circuit is disposed and the second power line area; and a second trench located between the second power line area and the display area.
12 . The display device of claim 9 , wherein: the plurality of clock signal lines comprise at least one of: at least one carry clock signal line for delivering the carry clock signal; at least one scan clock signal line for delivering the scan clock signal; and at least one sensing clock signal line for delivering the sensing clock signal; and at least one of the plurality of clock signal lines is located further outwardly from the display area than the at least one gate high voltage line.
13 . The display device of claim 10 , wherein: the plurality of clock signal lines comprise at least one of: at least one carry clock signal line for delivering the carry clock signal; at least one scan clock signal line for delivering the scan clock signal; and at least one sensing clock signal line for delivering the sensing clock signal, and at least one of the plurality of clock signal lines is located further outwardly from the display area than the at least one gate low voltage line.
14 . The display device of claim 9 , wherein at least one of the start signal line, the driving sequence control signal line, and the line selection signal line is located between at least one of the plurality of clock signal lines and the at least one gate high voltage line.
15 . The display device of claim 9 , wherein: the plurality of clock signal lines comprises at least one of: at least one carry clock signal line for delivering the carry clock signal; at least one scan clock signal line for delivering the scan clock signal; and at least one sensing clock signal line for delivering the sensing clock signal; and at least one of the scan clock signal line and the sensing clock signal line is located between the carry clock signal line and at least one of the start signal line, the driving sequence control signal line, and the line selection signal line.
16 . The display device of claim 1 , wherein: the carry output buffer comprises: a carry pull-up transistor connected between a carry clock node to which the carry clock signal is input and a carry output node from which the carry signal is output; and a carry pull-down transistor connected between a second gate low voltage node different from a first gate low voltage node and the carry output node; and the scan output buffer comprises: a scan pull-up transistor connected between a scan clock node to which the scan clock signal is input and a scan output node from which the scan signal is output; and a scan pull-down transistor connected between the first gate low voltage node and the scan output node.
17 . The display device of claim 16 , wherein the sensing output buffer comprises: a sensing pull-up transistor connected between a sensing clock node to which the sensing clock signal is input and a sensing output node from which the sensing signal is output; and a sensing pull-down transistor connected between the first gate low voltage node and the sensing output node.
18 . The display device of claim 17 , wherein the gate driving panel circuit comprises: a Q node to which respective gate nodes of the carry pull-up transistor, the scan pull-up transistor, and the sensing pull-up transistor are electrically connected; a QB node to which respective gate nodes of the carry pull-down transistor, the scan pull-down transistor, and the sensing pull-down transistor are electrically connected; and a logic block configured to control respective voltages of the Q node and the QB node.
19 . The display device of claim 1 , further comprising: at least one of a carry electrostatic discharge circuit electrically connected to a carry clock signal line for delivering the carry clock signal and a scan electrostatic discharge circuit electrically connected to a scan clock signal line for delivering the scan clock signal.
20 . The display device of claim 19 , wherein: the carry electrostatic discharge circuit comprises: at least one first diode connected between a point electrically connected to the carry clock signal line and an electrostatic discharge high level voltage node; and at least one second diode connected between the point electrically connected to the carry clock signal line and an electrostatic discharge low level voltage node; and the scan electrostatic discharge circuit comprises at least one third diode connected between a point electrically connected to the scan clock signal line and the electrostatic discharge high level voltage node.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of co-pending U.S. patent application Ser. No. 19/032,041, filed on Jan. 18, 2025, which is a continuation of U.S. patent application Ser. No. 18/585,820, filed on Feb. 23, 2024, now U.S. Pat. No. 12,243,493, issued on Mar. 4, 2025, which claims the priority benefit of Republic of Korea Patent Application No. 10-2023-0027297, filed on Feb. 28, 2023, in the Korean Intellectual Property Office. Each of the above prior U.S. and Republic of Korea patent applications is incorporated herein by reference for all purposes as if fully set forth herein. BACKGROUND Technical Field The present disclosure relates to electronic devices with a display, and more specifically, to a display panel and a display device. Description of the Related Art A display device may include a display panel in which a plurality of data lines and a plurality of gate lines are disposed, a data driving circuit for outputting data signals to the plurality of data lines, a gate driving circuit for outputting gate signals to the plurality of gate lines, and the like. In order for images to be displayed normally on the display device, gate signals are desired to be supplied normally through the plurality of gate lines. That is, in order to present images normally, it is necessary for gate driving to be performed normally. However, in a situation where gate driving is not performed normally, image quality may be degraded. SUMMARY One or more embodiments of the present disclosure may provide a gate driving panel circuit having a structure suitable for a gate-in-panel (GIP) type, and a display device including the gate driving panel circuit. One or more embodiments of the present disclosure may provide a display panel and a display device that have an effective electrostatic discharge structure. One or more embodiments of the present disclosure may provide a display panel and a display device that have a clock signal line arrangement structure that is advantageous to electrostatic discharge. One or more embodiments of the present disclosure may provide a display panel and a display device that have a scan pull-up transistor that is advantageous to electrostatic discharge. One or more embodiments of the present disclosure may provide a display device have a wiring structure for stably supplying various types of signals or power to a gate driving panel circuit disposed in a display panel. According to aspects of the present disclosure, a display device can be provided that includes a substrate including a display area in which images can be displayed and a non-display area different from the display area, a gate driving panel circuit disposed in the non-display area, configured to output a carry signal based on a carry clock signal, and configured to output a scan signal based on a scan clock signal, a carry clock signal line disposed in the non-display area and delivering the carry clock signal to the gate driving panel circuit, and a scan clock signal line disposed in the non-display area and delivering the scan clock signal to the gate driving panel circuit. The scan clock signal line may be located further outwardly than the carry clock signal line. The carry clock signal line may be located further outwardly than the gate driving panel circuit. The gate driving panel circuit may include an output buffer block including a scan output buffer for outputting the scan signal based on the scan clock signal and a carry output buffer for outputting the carry signal based on the carry clock signal, and a logic block for controlling operation of the output buffer block. The scan output buffer may include a scan pull-up transistor connected between a scan clock node to which the scan clock signal is input and a scan output node from which the scan signal is output, and a scan pull-down transistor connected between a first gate low voltage node and the scan output node. The carry output buffer may include a carry pull-up transistor connected between a carry clock node to which the carry clock signal is input and a carry output node from which the carry signal is output, and a carry pull-down transistor connected between a gate low voltage node different from the first gate low voltage node and the carry output node. The gate driving panel circuit includes a Q node to which respective gate nodes of the carry pull-up transistor and the scan pull-up transistor are electrically connected, and a QB node to which respective gate nodes of the carry pull-down transistor and the scan pull-down transistor are electrically connected. The logic block can control respective voltages of the Q node and the QB node. A channel width of the scan pull-up transistor may be greater than a channel width of the carry pull-up transistor. In one or more embodiments, the display device may further include a carry electrostatic discharge circuit electrically connected to the carry clock signal line, and a scan