US-20260128015-A1 - PROCESSOR, DISPLAY DEVICE INCLUDING THE PROCESSOR, AND ELECTRONIC DEVICE INCLUDING THE PROCESSOR

US20260128015A1US 20260128015 A1US20260128015 A1US 20260128015A1US-20260128015-A1

Abstract

A display device includes a pixel unit including pixels connected to data lines, gate lines, and light-emission control lines, a data driver which outputs a data voltage through output lines, a data distribution circuit which connects each of the output lines to an odd-numbered data line during a first sub-frame period and connects each of the output lines to an even-numbered data line during a second sub-frame period, a first gate driver which sequentially outputs a first gate signal to each of first gate lines during the first sub-frame period, a second gate driver which sequentially outputs a second gate signal to each of second gate lines during the second sub-frame period, and a light-emission control driver which divides the light-emission control lines into groups of four and output light-emission control signals in units of groups.

Inventors

Sehyuk PARK

Assignees

SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250905
Priority Date: 20241104

Claims (19)

1 . A display device comprising: a pixel unit including pixels connected to data lines, gate lines, and light-emission control lines; a data driver which outputs a data voltage through output lines; a data distribution circuit which connects each of the output lines to one of a pair of data lines in response to a first control signal during a first sub-frame period and connects each of the output lines to the other of the pair of data lines in response to a second control signal during a second sub-frame period; a first gate driver which sequentially outputs a first gate signal to each of first gate lines among the gate lines during the first sub-frame period; a second gate driver which sequentially outputs a second gate signal to each of second gate lines among the gate lines during the second sub-frame period; and a light-emission control driver which divides the light-emission control lines into groups of four and outputs light-emission control signals in units of groups.
2 . The display device of claim 1 , wherein the data distribution circuit connects each of the output lines to an odd-numbered data line among the pair of data lines during the first sub-frame period and connects each of the output lines to an even-numbered data line among the pair of data lines during the second sub-frame period.
3 . The display device of claim 2 , wherein pixels connected to the odd-numbered data lines are respectively connected to the first gate lines, and pixels connected to the even-numbered data lines are respectively connected to the second gate lines.
4 . The display device of claim 1 , wherein the data distribution circuit connects each of odd-numbered output lines among the output lines to an odd-numbered data line among the pair of data lines and connects each of even-numbered output lines from among the output lines to an even-numbered data line from among the pair of data lines during the first sub-frame period, and the data distribution circuit connects each of the odd-numbered output lines from among the output lines to the even-numbered data line among the pair of data lines and connects each of the even-numbered output lines among the output lines to the odd-numbered data line from among the pair of data lines during the second sub-frame period.
5 . The display device of claim 1 , wherein the pixel unit includes first pixels and second pixels, which are respectively connected to an odd-numbered data lines among the pair of data lines and alternately arranged in a column direction, and third pixels respectively connected to an even-numbered data lines among the pair of data lines and repeatedly arranged in the column direction, and the first pixels, the second pixels and the third pixels emit light of different colors, respectively.
6 . The display device of claim 5 , wherein the data driver alternately outputs a first data voltage and a second data voltage to each of the output lines in synchronization with an output timing of the first gate signal during the first sub-frame period, and outputs a third data voltage to each of the output lines in synchronization with an output timing of the second gate signal during the second sub-frame period.
7 . The display device of claim 5 , wherein the data driver alternately outputs a first color data voltage and a second color data voltage to each of odd-numbered output lines among the output lines in synchronization with an output timing of the first gate signal and outputs a third color data voltage to each of even-numbered output lines among the output lines in synchronization with an output timing of the first gate signal during the first sub-frame period, and the data driver outputs the third color data voltage to each of the odd-numbered output lines among the output lines in synchronization with the output timing of the second gate signal and alternately outputs the first color data voltage and the second color data voltage to each of the even-numbered output lines among the output lines in synchronization with the output timing of the second gate signal during the second sub-frame period.
8 . The display device of claim 1 , wherein the first gate driver sequentially outputs the first gate signal to each of the first gate lines in synchronization with an output timing of the first control signal during the first sub-frame period, and the second gate driver sequentially outputs the second gate signal to each of the second gate lines in synchronization with an output timing of the second control signal during the second sub-frame period.
9 . The display device of claim 1 , wherein the light-emission control driver outputs the light-emission control signals in synchronization with an output timing of a first light-emission control clock signal and an output timing of a second light-emission control clock signal delayed at a preset interval from the first light-emission control clock signal, an odd-numbered light-emission control signal among the light-emission control signals is output in synchronization with the output timing of the first light-emission control clock signal, and an even-numbered light-emission control signal among the light-emission control signals is output in synchronization with the output timing of the second light-emission control clock signal.
10 . The display device of claim 1 , wherein the light-emission control driver operates once during the first sub-frame period and operate once during the second sub-frame period, the light-emission control driver includes light-emission control stages connected to each other in a dependent manner, and each of the light-emission control stages is connected to a corresponding group of four light-emission control lines from among the light-emission control lines to simultaneously supply a corresponding light-emission control signal among the light-emission control signals thereto.
11 . A processor comprising: a graphics memory; an input circuit which receives an image signal and converts the image signal to generate image data; a first data processing circuit which stores the image data in the graphics memory according to an inputting order; and a second data processing circuit which reads pieces of sub-data corresponding to pixels driven during a first sub-frame period from the image data stored in the graphics memory and outputs the read-out pieces of sub-data to an output channel, and reads pieces of sub-data corresponding to pixels driven during a second sub-frame period and outputs the read-out pieces of sub-data to the output channel.
12 . The processor of claim 11 , wherein the first data processing circuit stores the image data in the graphics memory during a first period, the second data processing circuit reads the pieces of sub-data and output the read-out pieces of sub-data to the output channel during a second period, and a portion of the first period overlaps the second period.
13 . The processor of claim 12 , wherein a start timing of the second period is delayed by half a frame from a start timing of the first period.
14 . The processor of claim 11 , wherein the image data includes pieces of pixel pair data including two pieces of sub-data, the second data processing circuit reads pieces of odd-numbered sub-data from the pieces of pixel pair data and outputs the read-out pieces of odd-numbered sub-data to the output channel during the first sub-frame period, and the second data processing circuit reads pieces of even-numbered sub-data from the pieces of pixel pair data and outputs the read-out pieces of even-numbered sub-data to the output channel during the second sub-frame period.
15 . The processor of claim 11 , wherein the image data includes pieces of pixel pair data including two pieces of sub-data, the second data processing circuit reads pieces of odd-numbered sub-data from odd-numbered pieces of pixel pair data among the pieces of pixel pair data, reads pieces of even-numbered sub-data from even-numbered pieces of pixel pair data among the pieces of pixel pair data and outputs the read-out pieces of even-numbered sub-data to the output channel during the first sub-frame period, and the second data processing circuit reads pieces of even-numbered sub-data from the odd-numbered pieces of pixel pair data among the pieces of pixel pair data, reads pieces of odd-numbered sub-data from the even-numbered pieces of pixel pair data among the pieces of pixel pair data and outputs the read-out pieces of odd-numbered sub-data to the output channel during the second sub-frame period.
16 . An electronic device comprising: a display module; and a processor which controls the display module, wherein the processor comprises: a graphics memory; an input circuit which receives an image signal and converts the image signal to generate image data; a first data processing circuit which stores the image data in the graphics memory according to an inputting order; and a second data processing circuit which reads pieces of sub-data corresponding to pixels driven during a first sub-frame period from the image data stored in the graphics memory and outputs the read-out pieces of sub-data to an output channel, and reads pieces of sub-data corresponding to pixels driven during a second sub-frame period and outputs the read-out pieces of sub-data to the output channel.
17 . The electronic device of claim 16 , wherein the display module comprises: a pixel unit including pixels connected to data lines, gate lines, and light-emission control lines; a data driver which outputs a data voltage through output lines; output lines connected to the data driver; a data distribution circuit which connects each of the output lines to one of a pair of data lines in response to a first control signal during a first sub-frame period and connects each of the output lines to the other of the pair of data lines in response to a second control signal during a second sub-frame period; a first gate driver which sequentially outputs a first gate signal to each of first gate lines among the gate lines during the first sub-frame period; and a second gate driver which sequentially outputs a second gate signal to each of second gate lines among the gate lines during the second sub-frame period.
18 . The electronic device of claim 17 , wherein the display module further comprises a light-emission control driver which divides the light-emission control lines into groups of four and outputs light-emission control signals in units of groups.
19 . The electronic device of claim 17 , wherein the data distribution circuit connects each of the output lines to an odd-numbered data line among the pair of data lines during the first sub-frame period and connects each of the output lines to an even-numbered data line among the pair of data lines during the second sub-frame period, 20 . The electronic device of claim 17 , wherein the data distribution circuit connects each of odd-numbered output lines among the output lines to an odd-numbered data line among the pair of data lines and connects each of even-numbered output lines among the output lines to an even-numbered data line among the pair of data lines during the first sub-frame period, and the data distribution circuit connects each of the odd-numbered output lines among the output lines to the even-numbered data line among the pair of data lines and connects each of the even-numbered output lines among the output lines to the odd-numbered data line among the pair of data lines during the second sub-frame period.

Description

This application claims priority to Korean Patent Application No. 10-2024-0154710, filed on Nov. 4, 2024, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference. BACKGROUND 1. Field One or more embodiments relate to a processor, a display device including the processor, and an electronic device including the processor. 2. Description of the Related Art Display devices include a plurality of gate lines, a plurality of data lines, and a plurality of pixels located at intersections between the plurality of gate lines and the plurality of data lines. In order to apply a data voltage to each of the plurality of data lines, it is required that a data driver include a number of output lines corresponding to the number of data lines. As a plurality of integrated circuits are necessary, manufacturing costs of the display devices increase. SUMMARY One or more embodiments include a processor capable of preventing or reducing an increase in power consumption that may occur when the number of output lines is reduced, a display device including the processor, and an electronic device including the processor. However, aspects of embodiments are not limited thereto, and the above characteristics do not limit the scope of embodiments according to the disclosure. Additional aspects will be set forth in portion in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to one or more embodiments, a display device includes a pixel unit including pixels connected to data lines, gate lines, and light-emission control lines, a data driver which outputs a data voltage through output lines, a data distribution circuit which connects each of the output lines to one of a pair of data lines in response to a first control signal during a first sub-frame period and connects each of the output lines to the other of the pair of data lines in response to a second control signal during a second sub-frame period, a first gate driver which sequentially outputs a first gate signal to each of first gate lines from among the gate lines during the first sub-frame period, a second gate driver which sequentially outputs a second gate signal to each of second gate lines from among the gate lines during the second sub-frame period, and a light-emission control driver which divides the light-emission control lines into groups of four and outputs light-emission control signals in units of groups. In an embodiment, the data distribution circuit may connect each of the output lines to an odd-numbered data line from among the pair of data lines during the first sub-frame period and connect each of the output lines to an even-numbered data line from among the pair of data lines during the second sub-frame period. In an embodiment, pixels connected to the odd-numbered data lines may be connected to the first gate lines, and pixels connected to the even-numbered data lines may be connected to the second gate lines. In an embodiment, the data distribution circuit may connect each of odd-numbered output lines from among the output lines to an odd-numbered data line among the pair of data lines and connect each of even-numbered output lines from among the output lines to an even-numbered data line from among the pair of data lines during the first sub-frame period, and the data distribution circuit may connect each of the odd-numbered output lines from among the output lines to the even-numbered data line from among the pair of data lines and connect each of the even-numbered output lines from among the output lines to the odd-numbered data line among the pair of data lines during the second sub-frame period. In an embodiment, the data driver may output a data voltage in synchronization with an output timing of the first control signal during the first sub-frame period, and to output a data voltage in synchronization with an output timing of the second control signal during the second sub-frame period. In an embodiment, the pixel unit may include first pixels and second pixels, which are connected to an odd-numbered data line among the pair of data lines and alternately arranged in a column direction, and third pixels connected to an even-numbered data line from among the pair of data lines and repeatedly arranged in the column direction, where the first pixels, the second pixels and the third pixels may emit light of different colors, respectively. In an embodiment, the data driver may alternately output a first data voltage and a second data voltage to each of the output lines in synchronization with an output timing of the first gate signal during the first sub-frame period, and output a third data voltage to each of the output lines in synchronization with an output timing of the second gate signal during the second sub-frame period. In an embodiment, the data driv