US-20260128031-A1 - METHODS AND SYSTEMS FOR AUDIO PROCESSING

Abstract

A speaker and a microphone may be disposed in separate devices, wherein each of the digital to analog converter that is driving the speaker and the analog to digital converter that drives the microphone are driven by separate clocks. The speaker may be instructed to send (e.g., output) a pilot signal dedicated to synchronization. The microphone may detect the pilot signal, convert it to a digital signal, and an echo canceller (and/or resampler device) may use the digital signal output by the microphone to synchronize the clocks driving the digital to analog converter associated with the speaker device and the analog to digital converter associated with the microphone device. One or more packets containing audio samples may be sent to the speaker and the echo canceller as well as one or more packets sent to the echo canceller from the microphone device may be used to determine clock error.

Inventors

• Scott Kurtz
• Philip Stick
• Stephen Crowers

Assignees

• COMCAST CABLE COMMUNICATIONS, LLC

Dates

Publication Date

20260507

Application Date

20241105

Claims (20)

1. 1 . A method comprising: causing a first audio device to output an analog form of a pilot signal, wherein the first audio device is associated with a first clock; causing a second audio device to convert the analog form of the pilot signal to a detected pilot signal, wherein the second audio device is associated with a second clock; receiving, from the second audio device, the detected pilot signal; determining, based on a digital form of the pilot signal and the detected pilot signal, a clock error; and synchronizing, based on the clock error, the first clock and the second clock.
2. 2 . The method of claim 1 , wherein the pilot signal comprises one or more of an audible frequency, or an inaudible frequency, and wherein the first audio device comprises a speaker and the second audio device comprises a microphone.
3. 3 . The method of claim 1 , wherein the first clock is driven at the same frequency as the second clock, the method further comprising determining a phase trajectory difference between the digital form of the pilot signal and the detected pilot signal.
4. 4 . The method of claim 1 , wherein determining the clock error is based on one or more of a zero-cross frequency estimate or a phase trajectory offset estimate.
5. 5 . The method of claim 1 , wherein the first clock is associated with a first sample rate, wherein the second clock is associated with a second sample rate, and wherein the clock error indicates a difference between the first sampling rate and the second sampling rate.
6. 6 . The method of claim 1 , wherein synchronizing the first clock and the second clock comprises resampling one or more of the first clock or the second clock based on the clock error.
7. 7 . The method of claim 1 , further comprising: sending, to a first audio device, a digital form of the pilot signal; and causing the first audio device to convert the digital form of the pilot signal to the analog form of the pilot signal.
8. 8 . The method of claim 1 , further comprising performing echo cancellation based synchronizing the first clock and the second clock.
9. 9 . A method comprising: causing a first audio device to output an analog form of a pilot signal at a first frequency; receiving, from a second audio device, a digital form of the pilot signal, wherein the digital form of the pilot signal comprises a second frequency associated with a sampling rate; determining a difference between the first frequency and the second frequency; determining, based on the difference between the first frequency and the second frequency, a clock error; and updating, based on the clock error, the sampling rate.
10. 10 . The method of claim 9 , wherein the pilot signal comprises one or more of: an audible frequency or an inaudible frequency.
11. 11 . The method of claim 9 , wherein the first audio device comprises a speaker and is associated with a speaker clock and wherein the second audio device comprises a microphone and is associated with a microphone clock.
12. 12 . The method of claim 9 , wherein determining the clock error is based on a zero-cross frequency estimate.
13. 13 . The method of claim 9 , wherein determining the clock error is based on a phase trajectory offset estimate.
14. 14 . The method of claim 9 , further comprising performing echo cancellation based on the adjusted sampling rate.
15. 15 . A method comprising: causing a first audio device to output an analog form of a pilot signal at a first frequency; receiving, from a second audio device, a digital form of the pilot signal, wherein the digital form of the pilot signal comprises a second frequency associated with a sampling rate; determining, based on a difference between the first frequency and the second frequency, a clock error; receiving, from the second audio device, one or more samples of audio output by the first audio device; and buffering, based on the clock error, the one or more samples of audio.
16. 16 . The method of claim 15 , wherein the pilot signal comprises one or more of: an audible frequency or an inaudible frequency.
17. 17 . The method of claim 15 , wherein the first audio device comprises a speaker and is associated with a speaker clock and wherein the second audio device comprises a microphone and is associated with a microphone clock.
18. 18 . The method of claim 15 , wherein the clock error is associated with the second audio device.
19. 19 . The method of claim 15 , wherein determining the clock error is based on a zero-cross frequency estimate.
20. 20 . The method of claim 15 , further comprising performing echo cancellation.

Description

BACKGROUND Audio communication systems have become increasingly prevalent in various applications, from teleconferencing to voice-controlled devices. These systems often involve the use of microphones and speakers in close proximity, which can lead to acoustic feedback and echo issues. Echo occurs when a microphone picks up sound from a nearby speaker, causing the original audio to be re-transmitted and creating a distracting loop. To address this problem, audio echo cancellation techniques have been developed. These techniques typically involve analyzing the audio output from a speaker and subtracting any detected echo from the microphone input. However, effective echo cancellation relies on precise timing and synchronization between the speaker output and microphone input signals. In many audio systems, the speaker and microphone are driven by separate clocks. Over time, these clocks are subject to error and may drift relative to each other, leading to a misalignment between the speaker and microphone signals. This clock drift (or clock error) can significantly degrade the performance of echo cancellation algorithms, as they rely on accurate timing to identify and remove echo components. The issue of clock drift is particularly challenging in distributed audio systems, where the speaker and microphone may be physically separated and driven by independent clock sources. As the drift accumulates over time, it can lead to noticeable audio quality degradation and reduced effectiveness of echo cancellation. Existing approaches to addressing clock drift in audio systems often involve complex hardware solutions or frequent recalibration procedures. These methods can be costly, impractical for certain applications, or disruptive to the user experience. Additionally, some solutions may not be suitable for real-time audio processing, where low latency is critical. As audio communication continues to play an increasingly important role in various technologies, there is a growing need for improved methods of maintaining synchronization between audio components and ensuring robust echo cancellation performance in the presence of clock errors such as drift. SUMMARY It is to be understood that both the following general description and the following detailed description are exemplary and explanatory only and are not restrictive. Methods and systems for audio processing are described. An audio output device driven by a first clock may be configured to receive a first digital signal and convert and output the digital signal as a pilot tone. An audio detection device driven by a second clock may be configured to receive the pilot tone and send a digital version of the received pilot tone. A variation in the pilot tone may be used to determine a clock error between the first clock and second clock and corrective measures may be taken to synchronize the first clock and second clock. This summary is not intended to identify critical or essential features of the disclosure, but merely to summarize certain features and variations thereof. Other details and features will be described in the sections that follow. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments and together with the description, serve to explain the principles of the methods and systems: FIG. 1 shows an example system; FIGS. 2A-2B shows an example diagram of a device with speaker and microphone, its acoustic environment and a remote user who may experience echo; FIG. 3A shows an example diagram of analog to digital conversion; FIG. 3B shows an example diagram of digital to analog conversion; FIG. 4A shows an example method of analog to digital conversion and digital to analog conversion wherein the two conversions share the same clock; FIG. 4B shows an example method of analog to digital conversion and digital to analog conversion wherein the two conversions do not share the same clock; FIG. 5A shows an example method of analog to digital conversion and digital to analog conversion wherein the two conversions are clocked using different clocks; FIG. 5B shows an example of the effect of echo cancellation when speaker and microphone clocks are synchronized; FIG. 6A shows an example system and method for estimating clock difference using a zero crossing count method; FIG. 6B shows an example system and example method for estimating clock difference using phase trajectory estimation; FIGS. 7A-7E show example phase diagrams; FIG. 8 shows an example system that estimates clock error and corrects for it using a fractional sampling rate converter; FIGS. 9A-9B show example phase diagrams with samples indicated; FIG. 10 shows an example system comprising a buffer; FIG. 11 shows an example system for correcting long term error; FIG. 12 shows an example system; FIGS. 13A-13C show example error estimate diagrams; FIG. 14 shows an example system; FIG. 15 shows an example s