US-20260128063-A1 - SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

US20260128063A1US 20260128063 A1US20260128063 A1US 20260128063A1US-20260128063-A1

Abstract

A semiconductor device includes: a first stack including first material layers and second material layers that are alternately stacked; a penetration structure extending through the first stack and including an air gap; and a second stack located under the first stack and Including a key pattern located to correspond to the air gap.

Inventors

Jong Hoon Kim

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20250310
Priority Date: 20241105

Claims (19)

1 . A semiconductor device comprising: a first stack including first insulating layers and second insulating layers, the first insulating layers are alternately stacked with the second insulating layers in a vertical direction; a penetration structure extending in the vertical direction through the first stack and including an air gap; and a second stack located under the first stack and including a key pattern located to overlap with the air gap in the vertical direction.
2 . The semiconductor device of claim 1 , wherein the penetration structure comprises: an insulating liner; and the air gap located inside the insulating liner.
3 . The semiconductor device of claim 2 , further comprising: a metal pattern overlapping with the first stack in the vertical direction; and an interlayer insulating layer located between the first stack and the metal pattern.
4 . The semiconductor device of claim 3 , wherein the insulating liner and the interlayer insulating layer are a single layer that is integrally connected.
5 . The semiconductor device of claim 3 , further comprising a conductive pattern located between the first stack and the interlayer insulating layer.
6 . The semiconductor device of claim 5 , wherein the conductive pattern includes polysilicon.
7 . The semiconductor device of claim 1 , wherein the penetration structure comprises: a metal liner; an insulating liner surrounding the metal liner; and the air gap located inside the metal liner.
8 . The semiconductor device of claim 7 , wherein the metal liner protrudes from an upper surface of the first stack.
9 . The semiconductor device of claim 1 , wherein the second stack includes third material layers and fourth material layers, the third material layers alternately stacked with the fourth material layers in the vertical direction, and includes the key pattern on a surface of the second stack.
10 . The semiconductor device of claim 9 , wherein the third material layers and the fourth material layers are stacked in a shape in which they are recessed toward the penetration structure, and the key pattern includes a groove located in a recessed region.
11 . The semiconductor device of claim 1 , wherein the penetration structure has a smaller width at an upper portion of the penetration structure than at a lower portion of the penetration structure.
12 . The semiconductor device of claim 1 , wherein the penetration structure is located in a scribe lane region.
13 . The semiconductor device of claim 1 , further comprising: a memory cell array including a gate structure located at a level corresponding to the first stack and the second stack; a peripheral circuit; a bonding structure electrically connecting the memory cell array to the peripheral circuit.
14 . The semiconductor device of claim 1 , further comprising: a gate structure located at a level corresponding to the first stack and the second stack; a source layer overlapping with the gate structure in the vertical direction; and a metal wiring line located above the source layer.
15 . The semiconductor device of claim 14 , further comprising a metal pattern located over the first stack and located at a level corresponding to the metal wiring line.
16 . A semiconductor device comprising: a stack located in a scribe lane region and including first material layers and second material layers, the first material layers are alternately stacked with the second material layers in a vertical direction; a metal liner extending in the vertical direction through the stack; an insulating liner surrounding the metal liner; an air gap located inside the metal liner; and an interlayer insulating layer overlapping the stack in the vertical direction.
17 . The semiconductor device of claim 16 , further comprising a conductive pattern located between the stack and the interlayer insulating layer.
18 . The semiconductor device of claim 16 , further comprising a metal pattern overlapping with the interlayer insulating layer in the vertical direction and in contact with the air gap or the metal liner.
19 . The semiconductor device of claim 16 , wherein the insulating liner and the interlayer insulating layer are a single layer that is integrally connected.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119 (a) to Korean Patent Application No. 10-2024-0155194 filed on Nov. 5, 2024, in the Korean Intellectual Property Office, which application is incorporated herein by reference. BACKGROUND 1. Technical Field Embodiments of the present disclosure relate to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. 2. Related Art The degree of integration of a semiconductor device is mainly determined by an area occupied by a unit memory cell. Recently, as the improvement in the degree of integration of a semiconductor device for forming memory cells in a single layer on a substrate reaches a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been proposed. Furthermore, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed. SUMMARY In an embodiment, a semiconductor device may include: a first stack including first material layers and second material layers, the first insulating layers are alternately stacked with the second insulating layers in a vertical direction; a penetration structure extending in the vertical direction through the first stack and including an air gap; and a second stack located under the first stack and including a key pattern located to overlap with the air gap in the vertical direction. In an embodiment, a semiconductor device may include: a stack located in a scribe lane region and including first material layers and second material layers, the first material layers are alternately stacked with the second material layers in a vertical direction; a metal liner extending in the vertical direction through the stack; an insulating liner surrounding the metal liner; an air gap located inside the metal liner; and an interlayer insulating layer overlapping the stack in the vertical direction. In an embodiment, a method of manufacturing a semiconductor device may include: forming a first stack on a substrate; forming a first opening extending into the substrate through the first stack; forming a sacrificial layer in the first opening; forming a second stack on the first stack; etching the substrate so that the sacrificial layer is exposed; forming a second opening by removing the sacrificial layer; and forming an air gap in the second opening. In an embodiment, a method of manufacturing a semiconductor device may include: forming a stack; forming a contact plug penetrating through the stack; forming an opening extending through the stack; forming an insulating layer inside the opening and above the stack; forming a hard mask layer on the insulating layer to include an overhang structure in the opening; forming a mask pattern on the hard mask layer; forming a contact hole by etching the insulating layer using the mask pattern as an etching barrier, the contact hole exposing the contact plug; forming a via in the contact hole; and forming a metal liner in the opening, the metal liner including an air gap. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A, 1B, 1C, 1D, and 1E are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIGS. 2A and 2B are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIGS. 3A and 3B are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIGS. 4A, 4B, 4C, 4D, and 4E are diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment. FIGS. 5A, 5B, and 5C are diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment. FIGS. 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A and FIGS. 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, and 17B are diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment. FIG. 18 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. FIG. 19 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments are directed to a semiconductor device having a stable structure and improved characteristics and a manufacturing method of the semiconductor device. In an embodiment, by stacking memory cells in three dimensions, it is possible to improve the degree of integration of a semiconductor device. It is also possible, in an embodiment, to provide a semiconductor device having a stable structure and improved reliability. Hereafter, embodiments in accordance with the technical concept of the present disclosure will be described with reference to the accompanying drawings. Terms such as “first,” “second,” etc., are used to distinguish between vario