US-20260128064-A1 - SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

US20260128064A1US 20260128064 A1US20260128064 A1US 20260128064A1US-20260128064-A1

Abstract

According to one embodiment, a semiconductor memory device includes a first stacked body and a second stacked body in a first region. The semiconductor memory device includes a first via contact electrode in a second region adjacent to the first region and having a height that is at least half or more of a height of the first stacked body in the stacking direction, and a second via contact electrode disposed on the first via contact electrode in the stacking direction and electrically connected to the first via contact electrode and having a height that is at least half or more of the height of the second stacked body in the stacking direction. A diameter of a surface of the second via contact electrode facing the first via contact electrode is greater than a diameter of a surface of the first via contact electrode facing the second via contact electrode.

Inventors

Hiromasa YOSHIMORI

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260507
Application Date: 20250312
Priority Date: 20241107

Claims (20)

1 . A semiconductor memory device comprising: a first stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked in a first region in a stacking direction; a second stacked body in which a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked, the second stacked body disposed on the first stacked body in the stacking direction; a first via contact electrode disposed in a second region adjacent to the first region, the first via contact electrode having a height that is at least half or more of a height of the first stacked body in the stacking direction; and a second via contact electrode disposed on the first via contact electrode in the stacking direction and electrically connected to the first via contact electrode, the second via contact electrode having a height that is at least half or more of a height of the second stacked body in the stacking direction, wherein a diameter of a surface of the second via contact electrode facing the first via contact electrode is greater than a diameter of a surface of the first via contact electrode facing the second via contact electrode.
2 . The semiconductor memory device according to claim 1 , wherein when viewed from a direction orthogonal to the stacking direction, the first stacked body and the first via contact electrode overlap each other.
3 . The semiconductor memory device according to claim 1 , wherein when viewed from the stacking direction, the first via contact electrode and the second via contact electrode overlap each other.
4 . The semiconductor memory device according to claim 1 , further comprising: a third via contact electrode disposed in the second region and having a height that is greater than or equal to a sum of the height of the first stacked body and the height of the second stacked body in the stacking direction, wherein the third via contact electrode is spaced from the first via contact electrode and the second via contact electrode.
5 . The semiconductor memory device according to claim 1 , further comprising: a first chip including the first stacked body and the second stacked body; and a second chip bonded to the first chip at one or more bonding surfaces, wherein the second via contact electrode penetrates the one or more bonding surfaces of the first chip and the second chip.
6 . The semiconductor memory device according to claim 5 , wherein each of the first stacked body and the second stacked body includes a cell array, and the second chip includes a first CMOS circuit.
7 . The semiconductor memory device according to claim 5 , wherein the second via contact electrode has a height that is greater than a sum of the height of the second stacked body and a height of the second chip in the stacking direction.
8 . The semiconductor memory device according to claim 5 , wherein the second chip includes a diffusion prevention layer provided to surround the second via contact electrode.
9 . The semiconductor memory device according to claim 5 , further comprising: a third chip including a second CMOS circuit, wherein the third chip is bonded to a surface of the second chip opposite to the first chip, and the second via contact electrode is electrically connected to the third chip.
10 . The semiconductor memory device according to claim 9 , wherein the second via contact electrode has a height that is greater than a sum of the height of the second stacked body and a height of the second chip in the stacking direction.
11 . The semiconductor memory device according to claim 5 , further comprising: a third via contact electrode disposed in the second region and having a height that is greater than or equal to the sum of the height of the first stacked body and the height of the second stacked body in the stacking direction, wherein the third via contact electrode is spaced from the first via contact electrode and the second via contact electrode, and the third via contact electrode is electrically connected to the second chip.
12 . The semiconductor memory device according to claim 5 , wherein the second chip further includes a third stacked body in which a plurality of third conductive layers and a plurality of third insulating layers are alternately stacked in a third region, and a fourth stacked body in which a plurality of fourth conductive layers and a plurality of fourth insulating layers are alternately stacked, the fourth stacked body disposed on the third stacked body in the stacking direction, and each of the first stacked body, the second stacked body, the third stacked body, and the fourth stacked body includes a cell array.
13 . The semiconductor memory device according to claim 12 , wherein the second via contact electrode has a height that is greater than a sum of the height of the second stacked body, a height of the third stacked body, and a height of the fourth stacked body in the stacking direction.
14 . The semiconductor memory device according to claim 1 , further comprising: a conductive layer provided between the first via contact electrode and the second via contact electrode, wherein when viewed from the stacking direction, the conductive layer is circular or quadrilateral in shape, and at least one of a diameter of a surface of the conductive layer when viewed from the stacking direction or a distance between opposing sides of the conductive layer when viewed from the stacking direction, is greater than or equal to the diameter of the surface of the second via contact electrode facing the first via contact electrode.
15 . The semiconductor memory device according to claim 1 , further comprising: a diffusion prevention layer extending in the stacking direction and provided to surround the second via contact electrode.
16 . The semiconductor memory device according to claim 1 , wherein the second via contact electrode includes a material having a resistivity lower than a resistivity of the first via contact electrode.
17 . The semiconductor memory device according to claim 1 , wherein the second via contact electrode contains copper.
18 . The semiconductor memory device according to claim 1 , wherein the second via contact electrode has a height that is greater than the height of the second stacked body in the stacking direction.
19 . A manufacturing method of a semiconductor memory device, comprising: forming a first stacked body to include a plurality of first sacrifice layers and a plurality of first insulating layers that are alternately stacked in a first region; forming, in a second region adjacent to the first region, a first insulator having a height that is substantially the same as a height of the first stacked body in a stacking direction; forming a first memory hole in the first stacked body in the first region; forming a first via contact hole in the first insulator in the second region; embedding a first conductor in the first via contact hole to form a first via contact electrode; forming a second stacked body to include a plurality of second sacrifice layers and a plurality of second insulating layers that are alternately stacked on the first stacked body in the first region; forming, on the first insulator in the second region, a second insulator having a height that is substantially the same as a height of the second stacked body in the stacking direction; forming, in the second stacked body in the first region, a second memory hole connected to the first memory hole; forming a second via contact hole in the second insulator in the second region; and embedding a second conductor including a material different from the first via contact electrode in the second via contact hole to form a second via contact electrode that is electrically connectable with the first via contact electrode.
20 . The manufacturing method of a semiconductor memory device according to claim 19 , further comprising: after forming the first via contact electrode and before forming the second stacked body, forming a conductive layer electrically connectable with the first via contact electrode in the second region.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2024-195004, filed Nov. 7, 2024, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor memory device and a manufacturing method of the semiconductor memory device. BACKGROUND A three-dimensional structured semiconductor memory device is proposed in which on a substrate, a memory hole is formed on a stacked body with a plurality of layers of wiring layers through the insulating layer, and a silicon body is provided in the memory hole. In addition, a technology is proposed to provide a control circuit of the memory cell array of the three-dimensional structure directly under or directly above the memory cell array. DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating an example of a configuration of a semiconductor memory device according to a first embodiment; FIG. 2 is a perspective view illustrating an example of an appearance of the semiconductor memory device according to the first embodiment; FIG. 3A is a cross-sectional view illustrating an example of a configuration of the semiconductor memory device according to the first embodiment; FIG. 3B is a cross-sectional view illustrating an example of the configuration of the semiconductor memory device according to the first embodiment; FIG. 4A is a cross-sectional view illustrating an example of the configuration of the semiconductor memory device according to the first embodiment; FIG. 4B is a cross-sectional view illustrating an example of the configuration of the semiconductor memory device according to the first embodiment; FIG. 4C is a cross-sectional view illustrating an example of the configuration of the semiconductor memory device according to the first embodiment; FIG. 4D is a cross-sectional view illustrating an example of the configuration of the semiconductor memory device according to the first embodiment; FIG. 5 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of a memory layer according to the first embodiment; FIG. 6 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 7 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 8 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 9 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 10 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 11 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 12 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 13 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 14 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 15 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the memory layer according to the first embodiment; FIG. 16 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of a first CMOS layer according to the first embodiment; FIG. 17 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the first CMOS layer according to the first embodiment; FIG. 18 is a cross-sectional view illustrating an example of a cross-sectional structure during manufacturing of the first CMOS layer according to the first embodiment; FIG. 19 is a cross-sectional view illustrating an example of a bonding process of the memory layer and the first CMOS layer according to the first embodiment; FIG. 20 is a cross-sectional view illustrating an example of the bonding process of the memory layer and the first CMOS layer according to the first embodiment; FIG. 21 is a cross-sectional view illustrating an example of the bonding process of the memory layer and the first CMOS layer according to the first embodiment; FIG. 22 is a cross-sectional view illustrating an example of the bonding process of the memory layer and the first CMOS layer according to the first embodiment; FIG