US-20260128065-A1 - VERTICAL TWIST BITLINES WITH FOLDED BITLINE SENSE AMPLIFIER

US20260128065A1US 20260128065 A1US20260128065 A1US 20260128065A1US-20260128065-A1

Abstract

Provided are systems, methods, and apparatuses for vertical twist bitlines based on a folded bitline sense amplifier. The systems, devices, and methods include routing, at a first location, a first metal line from a first routing layer to a second routing layer, and a second metal line from the second routing layer to the first routing layer; connecting, within a first span starting at the first location, the second metal line to at least a first pair of vertical bitlines; routing, at a second location, the first metal line from the second routing layer to the first routing layer, and the second metal line from the first routing layer to the second routing layer; and connecting, within a second span starting at the second location, the first metal line to at least a second pair of vertical bitlines.

Inventors

Jongsik Na
Anthony Kanago
Sangmin Hwang

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250623

Claims (20)

1 . A method comprising: routing, at a first location, a first metal line from a first routing layer to a second routing layer of a stacked memory module, and a second metal line from the second routing layer to the first routing layer; connecting, within a first span starting at the first location, the second metal line to at least a first pair of vertical bitlines of the stacked memory module; routing, at a second location, the first metal line from the second routing layer to the first routing layer, and the second metal line from the first routing layer to the second routing layer; and connecting, within a second span starting at the second location, the first metal line to at least a second pair of vertical bitlines of the stacked memory module.
2 . The method of claim 1 , further comprising: connecting the first metal line to a sense amplifier of the stacked memory module based on routing, within the first span or a first subsequent span, a first via from the first metal line to the sense amplifier; and connecting the second metal line to the sense amplifier based on routing, within the second span or a second subsequent span, a second via from the second metal line to the sense amplifier.
3 . The method of claim 2 , wherein: a wordline of the stacked memory module shares a charge with the second via when the wordline is activated, and the first via is isolated from the charge of the wordline when the wordline is activated.
4 . The method of claim 2 , wherein: a wordline of the stacked memory module runs orthogonal to the first pair of vertical bitlines and the second pair of vertical bitlines, and the wordline runs orthogonal to the first metal line and the second metal line.
5 . The method of claim 2 , wherein: the stacked memory module includes multiple banks of vertical bitlines, and a first bank of the multiple banks includes the first pair of vertical bitlines, the second pair of vertical bitlines, the first routing layer, the second routing layer, the first via, the second via, and the sense amplifier.
6 . The method of claim 5 , wherein a second bank of the multiple banks runs parallel to the first bank and includes: a third pair of vertical bitlines connected to a third routing layer, a fourth pair of vertical bitlines connected to a fourth routing layer, a third via connecting the third routing layer to a second sense amplifier, and a fourth via connecting the fourth routing layer to the second sense amplifier.
7 . The method of claim 1 , wherein: a first set of wordlines are routed adjacent to a first bitline of the first pair of vertical bitlines, and connect, respectively, to a first set of memory cells connected to the first bitline, and a second set of wordlines are routed adjacent to the first bitline, and connect, respectively, to a second set of memory cells connected to the first bitline.
8 . The method of claim 1 , wherein: the first metal line is connected to M vertical bitlines, M being a positive integer and a multiple of two, the M vertical bitlines including the second pair of vertical bitlines, and the second metal line is connected to N vertical bitlines, N being a positive integer and a multiple of two, the N vertical bitlines including the first pair of vertical bitlines, N being greater than, less than, or equal to M.
9 . The method of claim 1 , wherein the first pair of vertical bitlines and the second pair of vertical bitlines run orthogonal to the first metal line and the second metal line.
10 . The method of claim 1 , wherein the first routing layer is beneath the second routing layer in the stacked memory module.
11 . A stacked memory module comprising: a first metal line routed, at a first location, from a first routing layer to a second routing layer of the stacked memory module, a second metal line routed, at the first location, from the second routing layer to the first routing layer; a first pair of vertical bitlines of the stacked memory module connected, within a first span starting at the first location, to the second metal line; the first metal line routed, at a second location, from the second routing layer to the first routing layer, and the second metal line routed, at the second location, from the first routing layer to the second routing layer; and a second pair of vertical bitlines of the stacked memory module connected, within a second span starting at the second location, to the first metal line.
12 . The stacked memory module of claim 11 , wherein the stacked memory module further comprises: a sense amplifier connected to the first metal line based on a first via that is routed, within the first span or a first subsequent span, from the first metal line to the sense amplifier; and the second metal line connected to the sense amplifier based on a second via that is routed, within the second span or a second subsequent span, from the second metal line to the sense amplifier.
13 . The stacked memory module of claim 12 , wherein the stacked memory module is configured to read a value stored in a memory cell connected to the first via, wherein reading the value is based on: the stacked memory module activating a wordline of the memory cell, and the sense amplifier detecting a voltage differential between the first via and the second via.
14 . The stacked memory module of claim 12 , wherein: the stacked memory module comprises a wordline that shares a charge with the second via when the wordline is activated, and the first via is isolated from the charge of the wordline when the wordline is activated.
15 . The stacked memory module of claim 12 , wherein: the stacked memory module comprises a wordline that runs orthogonal to the first pair of vertical bitlines and the second pair of vertical bitlines, and the wordline runs orthogonal to the first metal line and the second metal line.
16 . The stacked memory module of claim 12 , wherein: the stacked memory module includes multiple banks of vertical bitlines, and a first bank of the multiple banks includes the first pair of vertical bitlines, the second pair of vertical bitlines, the first routing layer, the second routing layer, the first via, the second via, and the sense amplifier.
17 . The stacked memory module of claim 11 , wherein: a first set of wordlines are routed adjacent to a first bitline of the first pair of vertical bitlines, and connect, respectively, to a first set of memory cells connected to the first bitline, and a second set of wordlines are routed adjacent to the first bitline, and connect, respectively, to a second set of memory cells connected to the first bitline.
18 . A fabrication system comprising: a routing controller to: route, at a first location, a first metal line from a first routing layer to a second routing layer of a stacked memory module, and a second metal line from the second routing layer to the first routing layer; connect, within a first span starting at the first location, the second metal line to at least a first pair of vertical bitlines of the stacked memory module; route, at a second location, the first metal line from the second routing layer to the first routing layer, and the second metal line from the first routing layer to the second routing layer; and connect, within a second span starting at the second location, the first metal line to at least a second pair of vertical bitlines of the stacked memory module.
19 . The fabrication system of claim 18 , wherein the fabrication system is further configured to: connect the first metal line to a sense amplifier of the stacked memory module based on the routing controller routing, within the first span or a first subsequent span, a first via from the first metal line to the sense amplifier; and connect the second metal line to the sense amplifier based on the routing controller routing, within the second span or a second subsequent span, a second via from the second metal line to the sense amplifier.
20 . The fabrication system of claim 19 , wherein: the fabrication system configures a wordline of the stacked memory module to share a charge with the second via when the wordline is activated, and the first via is isolated from the charge of the wordline when the wordline is activated.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application Ser. No. 63/725,539, filed Nov. 26, 2024, which is incorporated by reference herein for all purposes. TECHNICAL FIELD The disclosure relates generally to memory systems. In particular, the subject matter relates to vertical twist bitlines based on a folded bitline sense amplifier. SUMMARY Memory chips can include integrated circuits that store and retrieve data in digital devices, such as computers, mobile devices, etc. Memory chips can store data temporarily or permanently. Memory chips can include random-access memory (RAM), dynamic random-access memory (DRAM), read-only memory (ROM), flash memory, etc. Memory chips can include output lines that connect to a system data bus. A decoder can select a single memory chip for the microprocessor to access. Some memory chips may be cut from a wafer and placed in individual housings. Memory chips can be mounted to a printed circuit board (PCB), incorporated on a system on chip (SoC), stacked vertically, etc. The systems and methods described herein may be based on and/or may include stacked memory modules (e.g., 3D DRAM, vertically stacked (VS) DRAM). Stacked memory may use 3D stacking technology to increase the memory cell density of memory chips. The stacked memory modules can provide higher bandwidth, faster data transfer, and lower power consumption, which can help extend battery life for some devices (e.g., mobile devices). The systems and methods described herein may be based on and/or may include a bitline (BL), local bitline (LBL), and/or BL sense amplifier (SA). A given BLSA may connect to a BL of a memory chip and may detect and/or amplify relatively small voltage changes on the BL to accurately read the data stored in that memory cell (e.g., binary 0 or 1). The systems and methods described herein may be based on and/or may include a word line (WL). A voltage signal applied to a given WL may enable corresponding memory cells in that row to interact with bitlines, allowing data to be read from or written to that particular row. Thus, the WL may act as a control line to activate a specific set of memory cells within a memory array. In various embodiments, the systems and methods described herein include systems, methods, and apparatuses for vertical twist bitlines based on a folded bitline sense amplifier. In some embodiments, the described method comprises routing, at a first location, a first metal line from a first routing layer to a second routing layer and a second metal line in the reverse direction within a stacked memory module. The method further includes connecting, within a first span beginning at that location, the second metal line to at least a first pair of vertical bitlines; then routing, at a second location, the metal lines in reversed directions; and connecting, within a second span beginning at that second location, the first metal line to at least a second pair of vertical bitlines. In some embodiments, the method further includes establishing connections to a sense amplifier through a first via from the first metal line within the first or a subsequent span and a second via from the second metal line within the second or a subsequent span. Additional embodiments include configuring a wordline to share a charge with the second via when activated while ensuring isolation of the first via from such charge, orienting the wordline orthogonally to both the vertical bitlines and the metal lines, grouping multiple banks of vertical bitlines wherein one bank incorporates the metal lines, vias, and the sense amplifier, and routing sets of wordlines adjacent to the vertical bitlines to connect to corresponding sets of memory cells. In some embodiments, the first and second metal lines connect to M and N vertical bitlines respectively, with M and N being positive integers that are multiples of two (e.g., 2, 4, 6, 8, 10, 12, 14, 16, etc.). In other embodiments, the described technology provides a stacked memory module including a first metal line and a second metal line that are routed between a first routing layer and a second routing layer. At a first location, the second metal line is connected within a first span to a first pair of vertical bitlines, while at a second location the first metal line is connected within a second span to a second pair of vertical bitlines. In some embodiments, the module further comprises a sense amplifier that is connected via a first via from the first metal line and a second via from the second metal line, with the vias being routed within the respective spans or subsequent spans. The module may be configured to read stored values by activating a wordline so that a voltage differential between the vias is detected, and in alternative embodiments the wordline is designed to share a charge with one via while isolating the other, with the wordline oriented orthogonal to both the metal lines and the v