US-20260128066-A1 - SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device includes a semiconductor substrate and a memory cell array arranged in a first direction. The memory cell array includes a first region and a second region arranged in a second direction intersecting with the first direction, and a plurality of conductive layers include a first conductive layer, a third conducive layer and a second conductive layer in order from the closest to the semiconductor substrate. The first conductive layer is divided in the second direction to constitute a first divided layer and a second divided layer. The second conductive layer is divided in the second direction to constitute a third divided layer and a fourth divided layer. The third conductive layer is continuous over the first region and the second region. A plurality of wirings include a first wiring in the first region and a second wiring in the second region.

Inventors

• Shotaro HADA
• Shigeki Kobayashi
• Hiroshi Shinohara
• Hiroyasu Tanaka

Assignees

• KIOXIA CORPORATION

Dates

Publication Date

20260507

Application Date

20250903

Priority Date

20241105

Claims (20)

1. 1 . A semiconductor memory device comprising: a semiconductor substrate; and a memory cell array arranged at one side in a first direction intersecting with the semiconductor substrate with respect to the semiconductor substrate, wherein the memory cell array includes: a plurality of conductive layers extending in a second direction intersecting with the first direction and arranged in the first direction; a plurality of semiconductor layers extending in the first direction, arranged in a direction intersecting with the first direction, and facing the plurality of conductive layers; respective gate insulating films provided between the plurality of semiconductor layers and the plurality of conductive layers; and a plurality of wirings extending in a third direction intersecting with the first direction and the second direction, arranged in the second direction, and electrically connected to one end side in the first direction of the semiconductor layers, the memory cell array includes a first region and a second region arranged in the second direction, the plurality of conductive layers include: a first conductive layer closest to the semiconductor substrate; a second conductive layer farthest from the semiconductor substrate; and a third conductive layer provided between the first conductive layer and the second conductive layer, the first conductive layer is divided in the second direction to constitute a first divided layer positioned in the first region and a second divided layer positioned in the second region, the second conductive layer is divided in the second direction to constitute a third divided layer positioned in the first region and a fourth divided layer positioned in the second region, the third conductive layer is continuous over the first region and the second region, and the plurality of wirings include a first wiring positioned in the first region and a second wiring positioned in the second region.
2. 2 . The semiconductor memory device according to claim 1 , wherein the memory cell array includes a third region arranged in the second direction with the first region and the second region, and the memory cell array further includes a plurality of contact electrodes extending in the first direction in the third region, the plurality of contact electrodes have respective one ends electrically connected to the first divided layer, the second divided layer, the third divided layer, the fourth divided layer, and the third conductive layer, and the plurality of contact electrodes have respective the other ends electrically connected to the semiconductor substrate.
3. 3 . The semiconductor memory device according to claim 2 , wherein the memory cell array includes a terrace portion in which the first conductive layer, the second conductive layer, and the third conductive layer are formed in a staircase pattern in the third region, and the plurality of contact electrodes are connected to the terrace portion.
4. 4 . The semiconductor memory device according to claim 2 , wherein each of the plurality of contact electrodes includes: a columnar conductive layer extending in the first direction; and an insulating layer that covers a side surface of the conductive column.
5. 5 . The semiconductor memory device according to claim 2 , wherein the plurality of conductive layers and the plurality of semiconductor layers are divided in the third direction to constitute a plurality of blocks arranged in the third direction.
6. 6 . The semiconductor memory device according to claim 5 , wherein in the first conductive layer, each of the plurality of blocks is further divided in the third direction to constitute a plurality of string units arranged in the third direction.
7. 7 . The semiconductor memory device according to claim 5 , wherein respective a part of the plurality of contact electrodes are electrically connected to the second conductive layer and the third conductive layer for the respective blocks.
8. 8 . The semiconductor memory device according to claim 6 , wherein respective another part of the plurality of contact electrodes are electrically connected to the first conductive layer for the respective string units.
9. 9 . The semiconductor memory device according to claim 1 , wherein the semiconductor substrate includes: a first circuit that is able to apply different voltages to the first divided layer and the second divided layer and able to apply different voltages to the third divided layer and the fourth divided layer; and a second circuit that is able to separately read the first wiring and the second wiring.
10. 10 . The semiconductor memory device according to claim 6 , wherein the semiconductor substrate includes: a first circuit that is able to: apply voltages different for the respective blocks to the plurality of conductive layers; apply voltages different for the respective string units to the first conductive layer; apply different voltages to the first divided layer and the second divided layer; and apply different voltages to the third divided layer and the fourth divided layer; and a second circuit that is able to separately read the first wiring and the second wiring.
11. 11 . A semiconductor memory device comprising: a semiconductor substrate; a first memory chip arranged at one side in a first direction intersecting with the semiconductor substrate with respect to the semiconductor substrate; and a second memory chip arranged at a position farther from the semiconductor substrate than the first memory chip in a first memory chip side of the semiconductor substrate, wherein the first memory chip includes: a plurality of first conductive layers extending in a second direction intersecting with the first direction and arranged in the first direction; a plurality of first semiconductor layers extending in the first direction, arranged in a direction intersecting with the first direction, and facing the plurality of first conductive layers; respective first gate insulating films provided between the plurality of first semiconductor layers and the plurality of first conductive layers; and a plurality of first wirings extending in a third direction intersecting with the first direction and the second direction, arranged in the second direction, and electrically connected to one end side in the first direction of the first semiconductor layers, the second memory chip includes: a plurality of second conductive layers extending in the second direction and arranged in the first direction; a plurality of second semiconductor layers extending in the first direction, arranged in a direction intersecting with the first direction, and facing the plurality of second conductive layers; respective second gate insulating films provided between the plurality of second semiconductor layers and the plurality of second conductive layers; and a plurality of second wirings extending in the third direction, arranged in the second direction, and electrically connected to one end side in the first direction of the second semiconductor layers, the first memory chip and the second memory chip include a first region and a second region arranged in the second direction, the plurality of first conductive layers include: a third conductive layer closest to the semiconductor substrate; a fourth conductive layer farthest from the semiconductor substrate; and a fifth conductive layer provided between the third conductive layer and the fourth conductive layer, the plurality of second conductive layers include: a sixth conductive layer closest to the semiconductor substrate; a seventh conductive layer farthest from the semiconductor substrate; and an eighth conductive layer provided between the sixth conductive layer and the seventh conductive layer, the third conductive layer is divided in the second direction to be provided with a first divided layer positioned in the first region and a second divided layer positioned in the second region, the fourth conductive layer is divided in the second direction to be provided with a third divided layer positioned in the first region and a fourth divided layer positioned in the second region, the sixth conductive layer is divided in the second direction to be provided with a fifth divided layer positioned in the first region and a sixth divided layer positioned in the second region, the seventh conductive layer is divided in the second direction to be provided with a seventh divided layer positioned in the first region and an eighth divided layer positioned in the second region, each of the fifth conductive layer and the eighth conductive layer is continuous over the first region and the second region, the plurality of first wirings include a third wiring positioned in the first region and a fourth wiring positioned in the second region, and the plurality of second wirings include a fifth wiring positioned in the first region and a sixth wiring positioned in the second region.
12. 12 . The semiconductor memory device according to claim 11 , wherein the first memory chip and the second memory chip include a third region arranged in the second direction with the first region and the second region, and the first memory chip further includes a plurality of first contact electrodes extending in the first direction in the third region, the plurality of first contact electrodes have respective one ends electrically connected to the first divided layer, the second divided layer, the third divided layer, the fourth divided layer, and the fifth conductive layer, and the plurality of first contact electrodes have the other ends electrically connected to the semiconductor substrate, and the second memory chip further includes a plurality of second contact electrodes extending in the first direction in the third region, the plurality of second contact electrodes have respective one ends electrically connected to the fifth divided layer, the sixth divided layer, the seventh divided layer, the eighth divided layer, and the eighth conductive layer, and the plurality of second contact electrodes have the other ends electrically connected to the semiconductor substrate via the first memory chip.
13. 13 . The semiconductor memory device according to claim 12 , wherein the first memory chip further includes a plurality of third contact electrodes extending in the first direction in the third region, and respective first contact electrodes electrically connected to the third divided layer, the fourth divided layer, and the fifth conductive layer among the plurality of first contact electrodes are electrically connected to respective second contact electrodes electrically interconnected to the seventh divided layer, the eighth divided layer, and the eighth conductive layer among the plurality of second contact electrodes via the third contact electrodes, respectively.
14. 14 . The semiconductor memory device according to claim 13 , wherein second contact electrodes electrically connected to the fifth divided layer and the sixth divided layer among the plurality of second contact electrodes are electrically connected to the semiconductor substrate via the third contact electrodes without being connected to the first divided layer or the second divided layer, and first contact electrodes connected to the first divided layer and the second divided layer are electrically connected to the semiconductor substrate without being connected to the second contact electrode or the third contact electrode.
15. 15 . The semiconductor memory device according to claim 12 , wherein the plurality of first conductive layers and the plurality of first semiconductor layers, and the plurality of second conductive layers and the plurality of second semiconductor layers are each divided in the third direction to constitute a plurality of blocks arranged in the third direction.
16. 16 . The semiconductor memory device according to claim 15 , wherein in the third conductive layer and the sixth conductive layer, each of the plurality of blocks is further divided in the third direction to constitute a plurality of string units arranged in the third direction.
17. 17 . The semiconductor memory device according to claim 15 , wherein respective a part of the plurality of first contact electrodes are electrically connected to the fourth conductive layer and the fifth conductive layer for the respective blocks, and respective a part of the plurality of second contact electrodes are electrically connected to the seventh conductive layer and the eighth conductive layer for the respective blocks.
18. 18 . The semiconductor memory device according to claim 16 , wherein respective another part of the plurality of first contact electrodes are electrically connected to the third conductive layer for the respective string units, and respective another part of the plurality of second contact electrodes are electrically connected to the sixth conductive layer for the respective string units.
19. 19 . The semiconductor memory device according to claim 15 , wherein the semiconductor substrate includes: a first circuit that is able to apply different voltages to the first divided layer and the second divided layer, able to apply different voltages to the third divided layer and the fourth divided layer, able to apply different voltages to the fifth divided layer and the sixth divided layer, and able to apply different voltages to the seventh divided layer and the eighth divided layer; and a second circuit that is able to separately read the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring.
20. 20 . The semiconductor memory device according to claim 16 , wherein the semiconductor substrate includes: a first circuit that is able to: apply voltages different for the respective blocks to the plurality of first conductive layers and the plurality of second conductive layers; apply voltages different for the respective string units to the third conductive layer and the sixth conductive layer; apply different voltages to the first divided layer and the second divided layer; apply different voltages to the third divided layer and the fourth divided layer; apply different voltages to the fifth divided layer and the sixth divided layer; and apply different voltages to the seventh divided layer and the eighth divided layer; and a second circuit that is able to separately read the third wiring, the fourth wiring, the fifth wiring, and the sixth wiring.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of Japanese Patent Application No. 2024-193382, filed on Nov. 5, 2024, the entire contents of which are incorporated herein by reference. BACKGROUND Field Embodiments described herein relate generally to a semiconductor memory device. Description of the Related Art There has been known a semiconductor memory device that includes a substrate, a plurality of conductive layers stacked in a direction intersecting with a surface of this substrate, a semiconductor layer facing these plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layer. The gate insulating layer includes a memory portion that can store data, for example, an insulating electric charge accumulating layer of silicon nitride (SiN) or the like or a conductive electric charge accumulating layer such as a floating gate. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram illustrating a configuration of a memory die MD; FIG. 2 is a schematic circuit diagram illustrating a configuration of a part of the memory die MD; FIG. 3 is a schematic circuit diagram illustrating a configuration of a row decoder RD; FIG. 4 is a schematic circuit diagram illustrating a configuration of a sense amplifier module SAM; FIG. 5 is a schematic exploded perspective view illustrating an exemplary configuration of a semiconductor memory device according to a first embodiment; FIG. 6 is a schematic perspective view illustrating an exemplary configuration of a chip CM and a chip CP; FIG. 7 is a schematic bottom view of illustrating a configuration of a part of the chip CM when viewed in a direction of an arrow A in FIG. 6; FIG. 8 is a schematic cross-sectional view of a part of the chip CM taken along line B-B′ and viewed in an arrow direction in FIG. 7; FIG. 9 is a schematic cross-sectional view of a part of the chip CM taken along line C-C′ and viewed in an arrow direction in FIG. 7; FIG. 10 is a schematic cross-sectional view illustrating an enlarged part D in FIG. 9; FIG. 11 is a diagram schematically illustrating voltages applied to respective portions in a read operation of the memory die MD according to the first embodiment; FIG. 12 is a diagram schematically illustrating voltages applied to respective portions in another read operation of the memory die MD according to the first embodiment; FIG. 13 is a diagram schematically illustrating voltages applied to respective portions in another read operation of the memory die MD according to the first embodiment; FIG. 14 is a diagram schematically illustrating voltages applied to respective portions in another read operation of the memory die MD according to the first embodiment; FIG. 15 is a diagram schematically illustrating voltages applied to respective portions in a write operation of the memory die MD according to the first embodiment; FIG. 16 is a diagram schematically illustrating voltages applied to respective portions in an erase operation of the memory die MD according to the first embodiment; FIG. 17 is a cross-sectional view illustrating a schematic configuration of a semiconductor memory device according to a second embodiment; FIG. 18 is a block diagram illustrating a schematic configuration of a row decoder RD used in the second embodiment; FIG. 19 is a schematic exploded perspective view illustrating an exemplary configuration of a semiconductor memory device according to a third embodiment; FIG. 20 is a schematic perspective view illustrating an exemplary configuration of a chip CM1, a chip CM2, and a chip CP; FIG. 21 is a schematic circuit diagram illustrating a configuration of a part of the memory die MD; FIG. 22 is a schematic circuit diagram illustrating a configuration of a row decoder RD; FIG. 23 is a schematic block diagram illustrating a configuration of a sense amplifier module SAM; FIG. 24 is a schematic bottom view illustrating a configuration of a part of the chips CM1 and CM2 when viewed in a direction of an arrow E in FIG. 20; FIG. 25 is a schematic cross-sectional view of a part of the chips CM1 and CM2 taken along line F-F′ and viewed in an arrow direction in FIG. 24; FIG. 26 is a schematic cross-sectional view of a part of the chips CM1 and CM2 taken along line G-G′ and viewed in an arrow direction in FIG. 24; FIG. 27 is a diagram schematically illustrating voltages applied to respective portions of memory planes MP1, MP2 in a read operation of the memory die MD according to the third embodiment; FIG. 28 is a diagram schematically illustrating voltages applied to respective portions of the memory planes MP1, MP2 in another read operation; FIG. 29 is a diagram schematically illustrating voltages applied to respective portions of the memory planes MP1, MP2 in another read operation; FIG. 30 is a diagram schematically illustrating voltages applied to respective portions of the memory planes MP1, MP2 in another rea