US-20260128067-A1 - ELECTRONIC DEVICE COMPRISING A MEMORY ELEMENT

US20260128067A1US 20260128067 A1US20260128067 A1US 20260128067A1US-20260128067-A1

Abstract

The present disclosure relates to a memory device including a plurality of memory cells arranged in an array with word and bit lines. Each cell includes a memory element made of a phase-change material and two transistors connected by their first conduction nodes, themselves connected to a first terminal of the element. The elements of a bit line are connected by their second terminals. Both transistors of a word line are connected by their gates. Each cell is connected to two source lines, respectively, connected to the two second nodes of the transistors. The cells of a word line are connected to the two source lines and the cells of two consecutive word lines being connected to a common source line. Each transistor is disposed in and on a pair of two fins disposed in a semiconductor substrate.

Inventors

Olivier Weber

Assignees

STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date: 20260507
Application Date: 20251028
Priority Date: 20241107

Claims (20)

1 . A memory device, comprising: a plurality of memory cells arranged in an array with word lines and bit lines, each memory cell including: a memory element of a phase-change material and including a first terminal and a second terminal and two fin field-effect transistors for selecting the memory element, each transistor including first and second conduction nodes and a gate, wherein: both transistors of a same memory cell are connected to each other by their first conduction nodes, the first conduction nodes being connected to a first terminal of the memory element; the memory elements of a same bit line are all connected to each other by their second terminals; both transistors of memory cells of a same word line are all connected to each other by their gates; each memory cell is connected to two source lines, the two source lines being connected to the two second conduction nodes of the transistors of the memory cell, respectively, the memory cells of a same word line being connected to the same two source lines, and the memory cells of two consecutive word lines being connected to a common source line; and each transistor is disposed in and on a pair of two parallel and neighboring fins disposed in a semiconductor substrate.
2 . The memory device according to claim 1 , wherein the transistors of the memory cells of a same bit line are disposed on and in a same pair of two fins.
3 . The memory device according to claim 1 , wherein the fins of the same pair are spaced from 20 nm to 25 nm apart.
4 . The memory device according to claim 1 , wherein the fin pairs, in and on which are disposed the memory cells of two consecutive bit lines, are spaced from 60 nm to 65 nm apart.
5 . The memory device according to claim 1 , wherein the phase-change material is made of an alloy of germanium, antimony, and tellurium.
6 . The memory device according to claim 1 , wherein, within each memory cell, the memory element is separated from the transistors by an interconnecting stack.
7 . The memory device according to claim 6 , wherein each memory element is connected to the first conduction nodes of both transistors of the same memory cell through a conductive via passing through the interconnecting stack.
8 . The memory device according to claim 1 , wherein the memory element includes a heating metal resistive element disposed under the phase-change material and controlling this same material.
9 . The memory device according to claim 1 , wherein the source lines are, in top view, parallel to word lines.
10 . The memory device according to claim 1 , wherein the fins are disposed in a first region of the semiconductor substrate, the device further comprising other fins, regularly spaced, disposed in a second region of the semiconductor substrate.
11 . The memory device according to claim 1 , wherein fins of a same pair are closer together than fins of two neighboring pairs.
12 . A method for manufacturing a device including a plurality of memory cells arranged in an array with word lines and bit lines, each memory cell including a memory element made of a phase-change material and two fin field-effect transistors for selecting the memory element, each transistor comprising first and second conduction nodes and a gate, the memory element including two terminals, wherein: both transistors of a same memory cell are connected to each other by their first conduction nodes, the first conduction nodes being in turn connected to a first terminal of the memory element; the memory elements of a same bit line are all connected to each other by their second terminals; both transistors of the memory cells in a same word line are all connected to each other, by their gates; each memory cell is connected to two source lines, the two source lines being connected to two second conduction nodes of the transistors of the memory cell, respectively, the memory cells of a same word line being connected to the same two source lines, and the memory cells of two consecutive word lines being connected to a common source line, the method including the steps of: forming fins in a semiconductor substrate, fins being formed by pairs; epitaxially forming a semiconductive layer; and doping the semiconductive layer so as to form regions among which first regions correspond to source regions, and second regions correspond to drain regions, a drain region being common to both transistors of the same memory cell and a source region being common to two transistors of two neighboring memory cells.
13 . The method according to claim 12 , wherein the formation of the fins is carried out in a first region of the semiconductor substrate, the method further comprising, during the fins formation step, the formation of further regularly spaced fins in a second region of the semiconductor substrate.
14 . The method according to claim 12 , wherein fins of a same pair are closer together than fins of two neighboring pairs.
15 . A method, comprising: applying, in a memory array including a plurality of memory cells arranged in a plurality of bitlines and a plurality of wordlines, a first non-zero potential on a first bit line of the plurality of bitlines of a memory array and a zero potential on the other bit lines of the plurality of bitlines of the memory array, each memory cell including a memory element of a phase-change material and including a first terminal and a second terminal and two fin field-effect transistors for selecting the memory element, each transistor including first and second conduction nodes and a gate, wherein: both transistors of a same memory cell are connected to each other by their first conduction nodes, the first conduction nodes being connected to a first terminal of the memory element; the memory elements of a same bit line are all connected to each other by their second terminals; both transistors of memory cells of a same word line are all connected to each other by their gates; each memory cell is connected to two source lines, the two source lines being connected to the two second conduction nodes of the transistors of the memory cell, respectively, the memory cells of a same word line being connected to the same two source lines, and the memory cells of two consecutive word lines being connected to a common source line; and each transistor is disposed in and on a pair of two parallel and neighboring fins disposed in a semiconductor substrate; applying a second non-zero potential on a first word line of the plurality of wordlines and a zero potential on the other word lines of the plurality of wordlines; applying a zero potential to two source lines coupled to the memory cells of the first word line and a third non-zero potential to the other source lines.
16 . The method according to claim 15 , wherein the transistors of the memory cells of a same bit line are disposed on and in a same pair of two fins.
17 . The method according to claim 15 , wherein the fins of the same pair are spaced from 20 nm to 25 nm apart.
18 . The method according to claim 15 , wherein the fin pairs, in and on which are disposed the memory cells of two consecutive bit lines, are spaced from 60 nm to 65 nm apart.
19 . The method according to claim 15 , wherein the phase-change material is made of an alloy of germanium, antimony, and tellurium.
20 . The method according to claim 15 , wherein fins of a same pair are closer together than fins of two neighboring pairs.

Description

CROSS-REFERENCE TO PRIORITY APPLICATIONS This application claims the priority benefit of French patent application number FR2412188, filed on November 7, 2024, entitled “Dispositif électronique comprenant un circuit mémoire” which is hereby incorporated by reference to the maximum extent allowable by law. BACKGROUND Technical Field The present description relates generally to electronic devices and more particularly to electronic devices including a memory circuit. Description of the Related Art Electronic devices include both memory circuits and logic circuits. Here is more particularly of interest electronic devices including memory circuits, referred to as memory devices, including memory elements arranged in array, each memory element being associated to one or more selecting transistors. This transistor is used to separately program, erase, or read each memory element. It would be desirable to improve, at least in part, some aspects of the known electronic devices. BRIEF SUMMARY To this end, one embodiment provides a memory device including a plurality of memory cells arranged in an array with word lines and bit lines, each memory cell including a memory element made of a phase-change material and two fin field-effect transistors for selecting the memory element, each transistor including first and second conduction nodes and a gate, the memory element including two terminals, wherein: both transistors of a same memory cell are connected to each other by their first conduction nodes, said first conduction nodes being in turn connected to a first terminal of the memory element; the memory elements of a same bit line are all connected to each other by their second terminals; both transistors of memory cells of a same word line are all connected to each other, by their gates; each memory cell is connected to two source lines, the two source lines being connected to the two second conduction nodes of the transistors of the memory cell, respectively, the memory cells of a same word line being connected to the same two source lines, and the memory cells of two consecutive word lines being connected to a common source line; and each transistor is disposed in and on a pair of two parallel and neighboring fins disposed in a semiconductor substrate. According to an embodiment, the transistors of the memory cells of a same bit line are disposed on and in a same pair of two fins. According to an embodiment, the fins of the same pair are spaced from 20 nm to 25 nm apart, for example approximately 22 nm apart. According to an embodiment, the fin pairs, in and on which are disposed the memory cells of two consecutive bit lines, are spaced from 60 nm to 65 nm apart, for example approximately 62 nm apart. According to an embodiment, the phase-change material is made of an alloy of germanium, antimony, and tellurium. According to an embodiment, within each memory cell, the memory element is separated from the transistors by an interconnecting stack. According to an embodiment, each memory element is connected to the first conduction nodes of both transistors of the same memory cell through a conductive via passing through the interconnecting stack. According to an embodiment, the memory element includes a heating metal resistive element disposed under the phase-change material and controlling this same material. According to an embodiment, the source lines are, in tope view, parallel to word lines. According to an embodiment, the fins are disposed, in a first region of the semiconductor substrate, the device further including other fins, regularly spaced, disposed in a second region of the semiconductor substrate. Another embodiment provides a method for manufacturing a device including a plurality of memory cells arranged in an array with word lines and bit lines, each memory cell including a memory element made of a phase-change material and two fin field-effect transistors for selecting the memory element, each transistor including first and second conduction nodes and a gate, the memory element including two terminals, wherein: both transistors of a same memory cell are connected to each other by their first conduction nodes, said first conduction nodes being in turn connected to a first terminal of the memory element; the memory elements of a same bit line are all connected to each other by their second terminals; both transistors of the memory cells in a same word line are all connected to each other, by their gates; each memory cell is connected to two source lines, the two source lines being connected to two second conduction nodes of the transistors of the memory cell, respectively, the memory cells of a same word line being connected to the same two source lines, and the memory cells of two consecutive word lines being connected to a common source line, the method including the steps of: forming fins in a semiconductor substrate, fins being formed by pairs; epitaxially forming a semiconductive layer; and dopin