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US-20260128068-A1 - MEMORY DEVICE COMPRISING AN ARRAY OF MEMORY CELLS

US20260128068A1US 20260128068 A1US20260128068 A1US 20260128068A1US-20260128068-A1

Abstract

A memory device ( 100 ) comprising an array of memory cells ( 102.1 - 102.4 ) each comprising M memory elements ( 106 ) and a switch ( 104 ), the memory cells being addressed by word lines ( 108 ), source lines ( 112 ) and bit lines ( 110 ), wherein: a first conduction electrode of each switch is coupled to a first electrode of each of the memory elements of a single one of the memory cells; each word line is coupled to a control electrode of each switch of a single and same column of memory cells; each source line is coupled to a second conduction electrode of each switch of a single and same row of memory cells; each bit line is coupled to a second electrode of one of the memory elements of each memory cell of a single and same column of memory cells.

Inventors

  • Thomas BAUVENT
  • Gaël Pillonnet
  • Gabriel Molas

Assignees

  • Commissariat à l'Energie Atomique et aux Energies Alternatives

Dates

Publication Date
20260507
Application Date
20251101
Priority Date
20241105

Claims (15)

  1. 1 . A memory device comprising an array of memory cells, each memory cell comprising M memory elements, where M is an integer greater than or equal to 1, and a switch configured to pass or block a current between two conduction electrodes of the switch, the memory cells being addressed by word lines, source lines and bit lines, wherein: a first of the conduction electrodes of each switch is coupled to a first electrode of each of the memory elements of a single one of the memory cells; each word line is coupled to a control electrode of each switch of a single and same column of memory cells; each source line is coupled to a second of the conduction electrodes of each switch of a single and same row of memory cells; each bit line is coupled to a second electrode of one of the memory elements of each memory cell of a single and same column of memory cells.
  2. 2 . The memory device according to claim 1 , wherein each of the memory elements comprises a resistive portion and said memory element is of the OxRAM type, or comprises a solid electrolyte and said memory element is of the CBRAM type, or comprises a magnetoresistive stack and said memory element is of the MRAM type, or comprises a phase change material and said memory element is of the PCM type.
  3. 3 . The memory device according to claim 1 , wherein the switch of each memory cell comprises at least one MOS transistor and wherein the control electrode of the switch corresponds to the gate of the MOS transistor and the conduction electrodes of the switch correspond to the source and drain electrodes of the MOS transistor.
  4. 4 . The memory device according to claim 1 , wherein M bit lines are associated with each of the columns of memory cells, the bit lines being different from one column to another.
  5. 5 . The memory device according to claim 1 , wherein M is between 1 and 16.
  6. 6 . The memory device according to claim 1 , further comprising a control circuit configured to apply voltages to each of the bit lines, the word lines and the source lines.
  7. 7 . The memory device according to claim 6 , wherein the control circuit is configured to apply, during a write operation in at least one memory element of at least one of the memory cells of one of the columns of memory cells: a voltage V SET_SBL on the bit line coupled to said memory element; a voltage V SET_SSL on the source line coupled to the switch of said memory cell; a voltage V SET_UBL on the bit lines other than the one coupled to said memory element; a voltage V SET_USL on the source lines other than the one coupled to the switch of said memory cell; where V SET_SBL >V SET_USL >V SET_UBL ≥V SET_SSL .
  8. 8 . The memory device according to claim 7 , wherein, in a first configuration: the voltage V SET_SBL is equal to (3−α)·V L ; the voltage V SET_SSL is equal to 0; the voltage V SET_UBL is equal to V L ; the voltage V SET_USL is equal to approximately 2·V L ; or in which, in a second configuration: the voltage V SET_SBL is equal to approximately (2−α)·V L ; the voltage V SET_SSL is equal to 0; the voltage V SET_UBL is equal to approximately 0; the voltage V SET_USL is equal to approximately V L ; where V L corresponds to a value of a non-write limit voltage in said memory element, and α corresponds to an uncertainty factor due to the finite conductance of the switch of said memory cell and to the uncertainty of the conductance state of the M memory elements of said memory cell.
  9. 9 . The memory device according to claim 7 , wherein, during the write operation, the control circuit is configured to apply, to the word line coupled to the switch of said memory cell, a voltage for turning on the switch of said memory cell, and to the word lines other than the one coupled to the switch of said memory cell, a blocking voltage for blocking the switches coupled to these word lines.
  10. 10 . The memory device according to claim 6 , wherein the control circuit is configured to apply, during an erase operation in at least one memory element of at least one of the memory cells: a voltage V RESET_SBL on the bit line coupled to said memory element; a voltage V RESET_SSL on the source line coupled to the switch of said memory cell; a voltage V RESET_UBL on the bit lines other than the one coupled to said memory element; a voltage V RESET_USL on the source lines other than the one coupled to the switch of said memory cell; with V RESET_SSL >V RESET_UBL ≥V RESET_USL >V RESET_SBL .
  11. 11 . The memory device according to claim 10 , wherein, in a first configuration: the voltage V RESET_SBL is equal to 0; the voltage V RESET_SSL is equal to (3−α)·V L ; the voltage V RESET_UBL is equal to (2−α)·V L ; the voltage V RESET_USL is equal to (1−α)·V L ; or in which, in a second configuration: the voltage V RESET_SBL is equal to 0; the voltage V RESET_SSL is equal to 2·V L ; the voltage V RESET_UBL is equal to V L ; the voltage V RESET_USL is equal to approximately V L .
  12. 12 . The memory device according to claim 10 , in which, during the erase operation, the control circuit is configured to apply, to the word line coupled to the switch of said memory cell, a voltage that turns on the switch of said memory cell, and to the word lines other than the one coupled to the switch of said memory cell, a blocking voltage for blocking the switches coupled to these word lines.
  13. 13 . The memory device according to claim 6 , wherein the control circuit is configured to successively apply, during a read operation of several memory elements of each memory cell of one of the columns of the array, a non-zero voltage V R to each of the bit lines coupled to said memory elements, a zero voltage being applied to the bit line(s) coupled to the other memory elements; and further comprising a circuit for reading currents flowing in the source lines, configured to read these currents each time the voltage V R is applied to the bit lines coupled to said memory elements.
  14. 14 . The memory device according to claim 6 , wherein the control circuit is configured to apply, during a read operation of a memory element of each memory cell of one of the columns of the array, a non-zero voltage V R to the bit line coupled to said memory element, a zero voltage being applied to the bit line(s) coupled to the other memory elements; and further comprising a circuit for reading currents flowing in the source lines.
  15. 15 . The memory device according to claim 13 , further comprising a calculation circuit configured to determine information stored in each of the memory elements that are read from a conductance value of one of the switches, the value of the voltage V R and the values of the currents flowing in the source lines.

Description

FIELD The present disclosure relates generally to the field of electronic devices having an array of memory cells, including in particular resistive memory elements (known as RRAM or ReRAM for “Resistive Random-Access Memory”), for example based on oxide (of the OxRAM type for “Oxide-based Random-Access Memory”) or on a metal electrolyte (of the CBRAM type for “Conductive-Bridging Random-Access Memory”), or magnetoresistive memory elements (known as MRAM for “Magnetoresistive Random-Access Memory”), or comprising a phase-change material (known as PCM for “Phase-Change Material”). BACKGROUND The main block of a memory, or memory device, is generally formed by an array of memory cells, or “bitcells”. Each memory cell may include a selection switch, for example at least one selection transistor, for selecting and electrically accessing the memory cell, and at least one memory element, or memory point, in which information, for example a bit, is stored for the memory cell. In an RRAM memory cell, each memory element may comprise a portion of oxide or of metal electrolyte disposed between two electrodes. The document P. Polakowski et al., “Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications,” 2014 IEEE 6th International Memory Workshop (IMW), Taipei, Taiwan, 2014, pp. 1-4, describes such a configuration of an OxRAM memory cell. A memory cell can be programmed by using a single selection transistor coupled to one of the two electrodes of the memory element or of each memory element of the memory cell. Such a memory cell is referred to as 1TnR, where n corresponds to the number of memory elements in the cell. The memory cells are addressed by word lines, bit lines and source lines. The word lines are coupled to the memory cells in a perpendicular fashion to the bit lines so that the desired memory cells can be selected and addressed by using the word lines and the bit lines. The dimensions of a memory element are very small compared to those of a transistor. The storage density that can be achieved by such an array of memory cells is therefore limited by the dimensions of the transistors. It is possible to improve the storage density that can be achieved by providing, in each memory cell, several separate memory elements. However, as the number of memory elements per memory cell increases, various design constraints arise, such as those related to the floating nature of the nodes (connection between the memory elements and the selection transistor in each memory cell) other than the one selected during a write operation, to the reduced number of memory cells accessible in parallel or to stray currents that are proportional to the number of parallel accesses to memory cells. Different architectures of arrays of memory cells, called “crossbars,” have been provided. In these crossbar architectures, the selection of one of the memory cells is not performed by a transistor and the achievable storage density is greater. On the other hand, the selection of the memory cells for the implementation of the various read, write and erase operations is problematic because it involves complex nonlinear components. SUMMARY There is therefore a need to provide a memory device comprising an array of memory cells capable of achieving a high storage density without the disadvantages of known architectures and without a so-called “crossbar” architecture. An embodiment provides a solution to all or some of the disadvantages of the known solutions and provides a memory device comprising an array of memory cells, each memory cell comprising M memory elements, where M is an integer greater than or equal to 1, and a switch configured to pass or block a current between two conduction electrodes of the switch, the memory cells being addressed by word lines, source lines and bit lines, wherein: a first of the conduction electrodes of each switch is coupled to a first electrode of each of the memory elements of a single one of the memory cells;each word line is coupled to a control electrode of each switch of a single and same column of memory cells;each source line is coupled to a second of the conduction electrodes of each switch of a single and same row of memory cells; andeach bit line is coupled to a second electrode of one of the memory elements of each memory cell of a single and same column of memory cells. According to a particular embodiment, the bit lines are arranged substantially parallel to the word lines. According to a particular embodiment, each of the memory elements comprises a resistive portion and said memory element is of the OxRAM type or comprises a solid electrolyte and said memory element is of the CBRAM type or comprises a magnetoresistive stack and said memory element is of the MRAM type or comprises a phase change material and said memory element is of the PCM type. According to a particular embodiment, the switch of each memory cell comprises at least one MOS transistor and