US-20260128069-A1 - MEMORY DEVICE AND OPERATION METHOD THEREOF

Abstract

A memory device and an operation method thereof are provided. The operation method includes the following steps: receiving a writer mode command to operate the memory device to perform a data write operation by a system control logic; during a data write period of the data write operation, receiving and writing a plurality of word data into a memory buffer by the system control logic, and performing a data program operation by the memory buffer; and during a data program period of the data program operation, programming the plurality of word data into the memory cell by the memory buffer, wherein the data program period is partial overlapped with the data write period.

Inventors

• Johnny Chan
• Chi-Shun Lin

Assignees

• WINBOND ELECTRONICS CORP.

Dates

Publication Date

20260507

Application Date

20241103

Claims (20)

1. 1 . An operation method of a memory device, comprising: receiving a writer mode command to operate the memory device to perform a data write operation by a system control logic; during a data write period of the data write operation, receiving and writing a plurality of word data into a memory buffer by the system control logic, and performing a data program operation by the memory buffer; and during a data program period of the data program operation, programming the plurality of word data into the memory cell by the memory buffer, wherein the data program period is partial overlapped with the data write period.
2. 2 . The operation method according to claim 1 , wherein there is a data write clock latency between a start time of the write data period and a start time of the data program period.
3. 3 . The operation method according to claim 2 , wherein the data write clock latency is related to an error correction code word length.
4. 4 . The operation method according to claim 1 , wherein the plurality of word data comprise N word data, and when the system control logic receives and writes a second word data into the memory buffer in a current word cycle, the memory buffer also programs a first word data which received from a previous word cycle into the memory cell.
5. 5 . The operation method according to claim 4 , wherein when the system control logic finishes receiving and writing an N-th word data into the memory buffer, the memory buffer starts to program an (N-1)-th word data into the memory cell.
6. 6 . The operation method according to claim 5 , wherein the memory buffer programs the N-th word data into the memory cell after the data write operation is completed.
7. 7 . The operation method according to claim 1 , further comprising: receiving a chip select signal by a system control logic, wherein when a voltage level of the chip select signal is changed from a first voltage level to a second voltage level, the system control logic starts to receive the writer mode command, wherein when a voltage level of the chip select signal is changed from the second voltage level to the first voltage level, the system control logic finishes to receive and write the plurality of word data into the memory buffer.
8. 8 . The operation method according to claim 1 , further comprising: receiving a starting programming address by the system control logic, so that the memory buffer programs the plurality of word data into the memory cell according to the starting programming address.
9. 9 . The operation method according to claim 1 , wherein the step of receiving and writing the plurality of word data into the memory buffer by the system control logic comprises: generating a write word address to the memory buffer by an address counter, so that the memory device writes the plurality of word data into the memory buffer according to the write word address.
10. 10 . The operation method according to claim 1 , the step of programming the plurality of word data into the memory cell by the memory buffer comprises: generating a program word address to the memory buffer by an address counter, so that the memory device programs the plurality of word data into the memory cell from the memory buffer according to the program word address.
11. 11 . The operation method according to claim 10 , the step of programming the plurality of word data into the memory cell by the memory buffer further comprises: providing the program word address to a word line decoder and a bit line decoder of the memory cell by the address counter; and programing the plurality of word data into the memory cell of a memory array.
12. 12 . The operation method according to claim 1 , further comprising: generating a write control command and a program control command to the memory buffer by an address counter; assigning one of a first word buffer and a second word buffer of the memory buffer for performing the data write operation according to the write control command by the memory device; and assigning another one of the first word buffer and the second word buffer of the memory buffer for performing the data program operation according to the program control command by the memory device.
13. 13 . The operation method according to claim 12 , wherein the address counter comprises a plurality of flip-flops, and a data output terminal and an inverse data output terminal of one of the plurality of flip-flops is configured to output the write control command and the program control command.
14. 14 . The operation method according to claim 1 , wherein when the plurality of word data is read out from the memory cell, the system control logic executes an error correcting code operation.
15. 15 . The operation method according to claim 1 , wherein the memory device performs a normal program operation by using a first program bias voltage, and the memory device performs the data program operation by using a second program bias voltage, wherein the first program bias voltage is different from the second program bias voltage.
16. 16 . The operation method according to claim 15 , wherein the second program bias voltage is higher than the first program bias voltage.
17. 17 . The operation method according to claim 1 , wherein the plurality of word data comprises a system code.
18. 18 . The operation method according to claim 17 , wherein the system code is a boot-up code.
19. 19 . The operation method according to claim 1 , wherein the system control logic receive the plurality of word data through a serial peripheral interface or a quick path interconnect interface.
20. 20 . A memory device, comprising: a memory cell; a memory buffer, coupled to the memory cell; and a system control logic, coupled to the memory buffer, and configured to receive a writer mode command to operate the memory device to perform a data write operation, wherein during a data write period of the data write operation, the system control logic receives and writes a plurality of word data into the memory buffer, and the memory buffer performs a data program operation, wherein during a data program period of the data program operation, the memory buffer programs the plurality of word data into the memory cell, and the data program period is partial overlapped with the data write period.

Description

BACKGROUND Technical Field The disclosure relates a memory device, particularly, the disclosure relates to a memory device executes system code programming and an operation thereof. Description of Related Art In general, when the traditional memory device executes system code programming, the traditional memory device has to completely write the system code into the memory buffer firstly, and then program the system code into the memory cells according to the system code which is completely written into the memory buffer. Namely, the writing of the system code into the memory buffer ends before the beginning of programing the system code into the memory cells. That is to say, the traditional memory device needs to wait for the writing of the system code into the memory buffer to be completed before programming the system code into the memory cells. Therefore, reducing the required time to execute system code programming (hereinafter referred to as “required programming time”) is limited. In particular, if the system code is longer, the required programming time is also longer, and the required size of the memory buffer is also larger, which is harmful to operational efficiency and miniaturization. SUMMARY The disclosure provides a memory device and an operation method of the memory device to solve the above-mentioned problem. The operation method of the memory device of the disclosure includes the following steps: receiving a writer mode command to operate the memory device to perform a data write operation by a system control logic; during a data write period of the data write operation, receiving and writing a plurality of word data into a memory buffer by the system control logic, and performing a data program operation by the memory buffer; and during a data program period of the data program operation, programming the plurality of word data into the memory cell by the memory buffer, wherein the data program period is partial overlapped with the data write period. The memory device includes a memory cell, a memory buffer and a system control logic. The memory buffer is coupled to the memory cell. The system control logic is coupled to the memory buffer. The system control logic is configured to receive a writer mode command to operate the memory device to perform a data write operation. During a data write period of the data write operation, the system control logic receives and writes a plurality of word data into the memory buffer, and the memory buffer performs a data program operation. During a data program period of the data program operation, the memory buffer programs the plurality of word data into the memory cell, and the data program period is partial overlapped with the data write period. Based on the above, according to the memory device and the operation method thereof of the disclosure, the memory device can effectively reduce the time for system code programming, and also be conducive to miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a memory device according to an embodiment of the disclosure. FIG. 2 is a flow chart of an operation method of a memory device according to an embodiment of the disclosure. FIG. 3 is a schematic diagram of a memory device according to another embodiment of the disclosure. FIG. 4 is a schematic diagram of related signals according to the embodiment of FIG. 3 of the disclosure. FIG. 5 is a schematic diagram of a plurality of flip-flops according to another embodiment of the disclosure. DESCRIPTION OF THE EMBODIMENTS Reference will now be made in detail to the exemplary embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and the description to refer to the same or like components. The term “coupled” used throughout the whole specification of the present application (including the appended claims) may refer to any direct or indirect connection means. For example, if the text describes that a first device is coupled to a second device, it should be interpreted that the first device may be directly connected to the second device, or the first device may be indirectly connected through other devices or certain connection means to be connected to the second device. FIG. 1 is a schematic diagram of a memory device according to an embodiment of the disclosure. Referring to FIG. 1, the memory device 100 include a system control logic 110, a plurality of memory cells 120 and a memory buffer 130. The system control logic 110 is coupled to the memory cells 120, and the memory cells 120 are further coupled to the memory buffer 130. In the embodiment of the disclosure, the memory device 100 may be a NOR flash memory, but the disclosure is also not limited thereto. The system control logic 110 may receive a writer mode command 101 and a plurality of word data 102_1 to 102_N, where N is a positive integer. In the embodiment of t