US-20260128070-A1 - MEMORY APPARATUS

US20260128070A1US 20260128070 A1US20260128070 A1US 20260128070A1US-20260128070-A1

Abstract

A memory apparatus includes a domain crossing circuit including a plurality of first flip-flops operating based on the internal clock and a plurality of second flip-flops operating based on a data clock, the plurality of first flip-flops being initialized by the system domain reset signal, the plurality of second flip-flops being initialized by the data domain reset signal.

Inventors

Jong Hyuck CHOI
Sang Sic Yoon
Hyung Rok Do
Jeong Je Park
Joon Hong Park

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20250313
Priority Date: 20241104

Claims (16)

1 . A memory apparatus comprising: a timing control circuit configured to output a system domain reset signal and a data domain reset signal based on a system clock, and output the system clock as an internal clock when the system domain reset signal is output, an output timing of the system domain reset signal being different from an output timing of the data domain reset signal; and a domain crossing circuit comprising a plurality of first flip-flops operating based on the internal clock, and a plurality of second flip-flops coupled to the plurality of first flip-flops and operating based on a data clock, the plurality of first flip-flops being initialized by the system domain reset signal, the plurality of second flip-flops being initialized by the data domain reset signal.
2 . The memory apparatus of claim 1 , wherein the domain crossing circuit requires a pipe operation time from a time that the internal clock is received to a time that the data clock is received.
3 . The memory apparatus of claim 2 , wherein, in the timing control circuit, the output timing of the system domain reset signal is earlier than the output timing of the data domain reset signal.
4 . The memory apparatus of claim 3 , wherein, in the timing control circuit, the output timing of the system domain reset signal is earlier than a toggling timing of the data clock by the pipe operation time.
5 . The memory apparatus of claim 4 , wherein the timing control circuit is configured to generate the data domain reset signal by delaying the system domain reset signal.
6 . The memory apparatus of claim 5 , wherein the timing control circuit is configured to generate the system domain reset signal by delaying a CAS command by a first set period of the system clock, and generate the data domain reset signal by delaying the system domain reset signal by a second set period of the system clock different from the first set period of the system clock.
7 . The memory apparatus of claim 1 , wherein the domain crossing circuit further comprises: a plurality of pipe circuits configured to convert a first command based on the system clock into a second command based on the data clock which is based on outputs of the plurality of first flip-flops and the plurality of second flip-flops.
8 . The memory apparatus of claim 7 , wherein the system domain reset signal is input to a first terminal of one of the plurality of first flip-flops, and the system domain reset signal is input to second terminals of remaining flip-flops of the plurality of first flip-flops.
9 . The memory apparatus of claim 8 , wherein the data domain reset signal is input to a first terminal of one of the plurality of second flip-flops, and the data domain reset signal is input to second terminals of remaining flip-flops of the plurality of second flip-flops.
10 . The memory apparatus of claim 9 , wherein initialization of the plurality of first flip-flops and initialization of the plurality of second flip-flops are such that the flip-flop receiving the system domain reset signal or the data domain reset signal through the first terminal outputs a level different from levels of the remaining flip-flops.
11 . The memory apparatus of claim 10 , wherein input and output structures of the plurality of first flip-flops and the plurality of second flip-flops are ring structures.
12 . A memory apparatus comprising: a command decoding circuit configured to output a read and write (read/write) command and a column address strobe (CAS) command synchronized to a system clock; a timing control circuit configured to output a system domain reset signal, a data domain reset signal, and an internal clock based on the CAS command and the system clock, and output a delayed read/write command based on the system clock and the read/write command; and a domain crossing circuit configured to synchronize the delayed read/write command with a data clock and output a data input and output (input/output) command under control of the system domain reset signal, the data domain reset signal, and the internal clock.
13 . The memory apparatus of claim 12 , wherein the timing control circuit is further configured to output the system domain reset signal at a timing earlier than an output timing of the data domain reset signal.
14 . The memory apparatus of claim 13 , wherein the timing control circuit is further configured to output the system domain reset signal based on the CAS command and the system clock, output the system clock as the internal clock when the system domain reset signal is output, and output, as the data domain reset signal, the delayed system domain reset signal generated by delaying the system domain reset signal.
15 . The memory apparatus of claim 14 , wherein, in the domain crossing circuit, a reception timing of the internal clock is earlier than a reception timing of the data clock.
16 . The memory apparatus of claim 15 , wherein the domain crossing circuit is further configured to toggle the data clock after the internal clock is received and a pipe operation time elapses.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2024-0154294 filed on Nov. 4, 2024, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field Embodiments of the present disclosure relate to an integrated circuit technology, and more particularly, to a memory apparatus. 2. Related Art Recently, with the miniaturization, low power consumption, high performance, diversification, and the like of electronic devices, there is a demand for memory apparatuses capable of storing information in various electronic devices such as computers and portable communication devices. In order to implement high performance, a memory apparatus that inputs and outputs data at a high speed is being developed to use a system clock for receiving addresses and commands and a data clock for inputting and outputting data. In this way, the memory apparatus using heterogeneous clocks requires a domain crossing circuit that can synchronize the heterogeneous clocks. For example, a domain crossing circuit that synchronizes a command synchronized to the system clock to the data clock is required. SUMMARY In an embodiment of the present disclosure, a memory apparatus includes a timing control circuit that outputs a system domain reset signal and a data domain reset signal based on a system clock, and outputs the system clock as an internal clock when the system domain reset signal is output, an output timing of the system domain reset signal being different from an output timing of the data domain reset signal; and a domain crossing circuit including a plurality of first flip-flops operating based on the internal clock and a plurality of second flip-flops operating based on a data clock, the plurality of first flip-flops being initialized by the system domain reset signal, the plurality of second flip-flops being initialized by the data domain reset signal. In an embodiment of the present disclosure, a memory apparatus includes a command decoding circuit that outputs a read/write command and a CAS command synchronized to a system clock; a timing control circuit that outputs a system domain reset signal, a data domain reset signal, and an internal clock based on the CAS command and the system clock, and outputs a delayed read/write command based on the system clock and the read/write command; and a domain crossing circuit that synchronizes the delayed read/write command with a data clock and outputs a data input/output command under control of the system domain reset signal, the data domain reset signal, and the internal clock. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for describing the configuration of a memory apparatus in accordance with an embodiment of the present disclosure. FIG. 2 is a diagram for describing the configuration of a timing control circuit included in the memory apparatus in accordance with an embodiment of the present disclosure. FIG. 3 is a diagram for describing the configuration of a domain crossing circuit included in the memory apparatus in accordance with an embodiment of the present disclosure. FIG. 4 is a timing diagram for describing the operation of the memory apparatus in accordance with an embodiment of the present disclosure. FIG. 5 is a diagram for describing the configuration of a memory apparatus in accordance with another embodiment of the present disclosure. FIG. 6 is a diagram for describing the configuration of a timing control circuit included in the memory apparatus in accordance with another embodiment of the present disclosure. FIG. 7 is a diagram for describing the configuration of a domain crossing circuit included in the memory apparatus in accordance with another embodiment of the present disclosure. FIG. 8 is a timing diagram for describing the operation of the memory apparatus in accordance with another embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments of the present disclosure are directed to a memory apparatus that provides a system clock to a domain crossing circuit at an earlier timing compared to a data clock. The operation reliability of a memory apparatus can be improved. Hereafter, embodiments in accordance with the technical spirit of the present disclosure are described with reference to the accompanying drawings. A memory apparatus is configured to store data and output the stored data. For example, the memory apparatus receives a command for storing data received from an external device (for example, a memory controller) or outputting the stored data, and receives data from the external device or outputs the stored data to the external device. In such a case, the memory apparatus receives a command in synchronization with a system clock and outputs the stored data in synchronization with a data clock. Accordingly, the memory apparatus includes a domain crossing circuit for the system clock and the data clock. It is noted that