US-20260128071-A1 - MEMORY DEVICE AND METHOD FOR SYNCHRONIZING COMMAND START POINT (CSP)

Abstract

Provided are a memory device and a method for command start point (CSP) synchronization. The memory device includes: a control logic circuit configured to receive command address (CA) signals and control an operation of the memory device; a clock circuit configured receive a clock signal and divide the clock signal to generate first to fourth phase clock signals that are respectively synchronized with first to fourth rising edges of the CA signals indicating a command start point (CSP) command, wherein the first to fourth rising edges of the CA signals constitute a command window; and a CA parity circuit configured to perform a command address parity (CAPAR) checking operation on the CSP command, wherein the CAPAR checking operation includes a plurality of operations respectively corresponding to rolling windows in which the command window is delayed by one clock cycle of the clock signal.

Inventors

• Hyeran KIM
• Taeyoung Oh

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20260102

Priority Date

20230202

Claims (20)

1. 1 . A memory device comprising: a control logic circuit configured to receive command address (CA) signals and control an operation of the memory device; a clock circuit configured receive a clock signal from a memory controller and divide the clock signal to generate first to fourth phase clock signals that are respectively synchronized with first to fourth rising edges of the CA signals indicating a command start point (CSP) command, wherein the first to fourth rising edges of the CA signals constitute a command window; and a CA parity circuit configured to perform a command address parity (CAPAR) checking operation on the CSP command, wherein the CAPAR checking operation comprises a plurality of operations respectively corresponding to rolling windows in which the command window is delayed by one clock cycle of the clock signal.
2. 2 . The memory device of claim 1 , wherein the CA parity circuit is further configured to transmit an error signal indicating that a CA parity error has been identified in the CAPAR checking operation to the memory controller outside the memory device.
3. 3 . The memory device of claim 2 , wherein the CA parity circuit is further configured to transmit the error signal as one of three voltage levels in a pulse amplitude modulation-3 (PAM-3) signal.
4. 4 . The memory device of claim 2 , wherein the memory controller is configured to perform CA bus training on the memory device based on the error signal.
5. 5 . The memory device of claim 4 , wherein the memory device is configured to receive a next CSP command after the CA bus training is performed by the memory controller.
6. 6 . The memory device of claim 1 , wherein the CA parity circuit is further configured to, based on no CA parity error being identified in the CAPAR checking operation, identify a window comprising operands which correspond to those of the CSP command from among the rolling windows as the command window and synchronize a first rising edge of the command window with a start point of the CSP command.
7. 7 . The memory device of claim 6 , wherein the memory device is configured to align a command boundary with the start point of the CSP command and decode the CA signals within the command boundary.
8. 8 . The memory device of claim 1 , wherein the CA parity circuit comprises: a CA sampler circuit configured to latch the CA signals in response to each of first to fourth final phase clock signals; a parity calculating circuit configured to perform the CAPAR checking operation on the CA signals latched by the CA sampler circuit included in each of the rolling windows; a CSP check circuit configured to identify a window comprising operands which correspond to those of the CSP command with respect to the CA signals latched by the CA sampler circuit included in each of the rolling windows as the command window; a CSP encode circuit configured to synchronize a first rising edge of the command window with a start point of the CSP command; and a CSP-synchronized selection circuit configured to receive the first to fourth phase clock signals, select a phase clock signal synchronized with the start point of the CSP command from among the first to fourth phase clock signals, and output the first to fourth final phase clock signals based on the selected phase clock signal.
9. 9 . A memory device comprising: a control logic circuit configured to receive command address (CA) signals and control an operation of the memory device; a clock circuit configured receive a clock signal and divide the clock signal to generate first to fourth phase clock signals that are respectively synchronized with first to fourth rising edges of the CA signals indicating an error pattern, wherein the first to fourth rising edges of the CA signals constitute a command window; and a CA parity circuit configured to perform a command address parity (CAPAR) checking operation on the error pattern, wherein the CAPAR checking operation comprises a plurality of operations respectively corresponding to rolling windows in which the command window is delayed by one clock cycle of the clock signal.
10. 10 . The memory device of claim 9 , wherein the CA parity circuit is further configured to transmit an error signal indicating that a CA parity error has been identified in the CAPAR checking operation to a memory controller outside the memory device.
11. 11 . The memory device of claim 10 , wherein the CA parity circuit is further configured to transmit the error signal as one of three voltage levels in a pulse amplitude modulation-3 (PAM-3) signal.
12. 12 . The memory device of claim 10 , wherein the memory controller is configured to perform CA bus training on the memory device based on the error signal, and the error signal is not an error signal expected by the memory controller.
13. 13 . The memory device of claim 12 , wherein the memory device is configured to receive a command start point (CSP) command after the CA bus training is performed by the memory controller.
14. 14 . The memory device of claim 10 , wherein the memory device is configured to receive a command start point (CSP) command from the memory controller, and the error signal is an error signal expected by the memory controller.
15. 15 . The memory device of claim 14 , wherein the memory device is configured to align a command boundary with a start point of the CSP command and decode the CA signals within the command boundary.
16. 16 . A method of operating a memory device, the method comprising: receiving a clock signal; dividing the clock signal to generate first to fourth phase clock signals that are respectively synchronized with first to fourth rising edges of command address (CA) signals, wherein the first to fourth rising edges of the CA signals constitute a command window; receiving the CA signals from a memory controller outside the memory device; performing a command address parity (CAPAR) checking operation on the CA signals, wherein the CAPAR checking operation comprises a plurality of operations respectively corresponding to rolling windows in which the command window is delayed by one clock cycle of the clock signal; and transmitting an error signal indicating a CA parity error is identified in the CAPAR checking operation to the memory controller.
17. 17 . The method of claim 16 , wherein the CA signals comprise a command start point (CSP) command.
18. 18 . The method of claim 17 , further comprising: identifying a window comprising operands which correspond to those of the CSP command from among the rolling windows as the command window; and synchronizing a first rising edge of the command window with a start point of the CSP command.
19. 19 . The method of claim 16 , wherein the CA signals comprise an error pattern which intentionally causes the CA parity error by the memory controller.
20. 20 . The method of claim 19 , wherein any one of the CA signals is applied as a logic 0 operand at first to third rising edges of the command window to indicate the error pattern, and is calculated as an odd value in the CAPAR checking operation.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a Continuation Application of U.S. application No. Ser. No. 18/529,876, filed on Dec. 5, 2023, which claims priority to Korean Patent Application Nos. 10-2023-0014444, filed on Feb. 2, 2023, 10-2023-0057365, filed on May 2, 2023, and 10-2023-0126401, filed on Sep. 21, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND The present disclosure relates to semiconductor memory devices, and more particularly, to a memory device that synchronizes a command start point (CSP) with a clock by performing a command address (CA) parity checking operation and a method of operating the same. Due to demands for increased operating speed, increased data capacity, and decreased power consumption of electronic systems, semiconductor memories that may be accessed faster, store more data, and consume less power are continuously being developed. A semiconductor memory is generally controlled by providing commands, addresses, and clocks to a memory device. Various commands, addresses, and clocks may be provided by, for example, a memory controller. Commands may control the memory device to perform various memory operations, e.g., a read operation for retrieving data from the memory device and a write operation for storing data in the memory device. Data associated with commands may be provided between the memory controller and the memory device at known timings relative to reception and/or transmission by the memory device. A clock (e.g., WCK) provided to the memory device may be used to generate an internal clock signal that controls timings of various internal circuits during a memory operation. The memory device may capture signals received from the memory controller in response to a WCK clock, e.g., a command address CA signal, data DQ, etc., and synchronize data DQ to be transmitted to the memory controller with a clock signal (e.g., RCK). It is important for the memory device to accurately capture transmitted signals as the frequency of a WCK clock provided from the memory controller increases in accordance with the demand for a high data transfer rate. A bus training mode may be provided between the memory controller and the memory device to capture command address CA signals and data DQ based on a WCK clock having a high frequency. The memory controller may perform bus interface training on a CA bus and/or a DQ bus when power is supplied to the memory device or when a specific condition is satisfied. For example, a CA bus training may be performed when the memory device is in a reset state during power-up initialization by using a CA Training Entry (CATE) command, or when a CA parity error occurs. In CA bus training, the memory controller may transmit a command bus training (CBT) pattern to the memory device through a CA bus, compare an output pattern of the memory device received through a DQ bus with the CBT pattern, adjust the timing of a CA signal carrying a CA pattern until the output pattern becomes identical to the CBT pattern, and determine whether the CA signal is accurately captured by the memory device. For example, the memory controller may determine the CA signal is accurately captured by the memory device when output pattern becomes identical to the CBT pattern. When the CA bus training is completed, the memory controller may issue a command start point (CSP) command synchronized with a WCK clock to the memory device to instruct the memory device to prepare for a memory operation. When the memory controller issues a command including a CSP command to the memory device, the memory controller may provide command operands, for example, for 4*tWCK, which corresponds to four WCK clock cycles. In this regard, command operands may be provided to a CA signal (e.g., CA[4:0]) line at a first rising edge, a second rising edge, a third rising edge, and a fourth rising edge of a WCK clock. Four WCK clock cycles in which command operands are applied may be aligned with a command boundary (e.g., CB of FIG. 4B). The memory controller may issue a CSP command to the memory device to prepare the memory device for a memory operation after the memory device exits a sleep state. The memory device may perform a CA parity (CAPAR) checking operation in order to improve signal integrity of a CA signal line. For example, during the CAPAR checking operation, a parity is generated by calculating the sum of CA[4:0] signal bits for a CB recognized as 4 WCK clock cycles in which a CSP command is applied, it is determined whether a calculated parity value is, for example, an even value, and, when the calculated parity value is not an even value, the memory controller is notified that there is an error in the CA[4:0] signal bits indicating the CSP command. When there is an error in the CSP command, the memory controller may perform CA bus training with the memory device again and, upon compl