US-20260128072-A1 - SYSTEMS AND METHODS FOR SCAN CHAIN INTERFACE FOR NON-VOLATILE STORAGE BITS

US20260128072A1US 20260128072 A1US20260128072 A1US 20260128072A1US-20260128072-A1

Abstract

A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.

Inventors

Syed M. Alam
Jacob T. Williams

Assignees

EVERSPIN TECHNOLOGIES, INC.

Dates

Publication Date: 20260507
Application Date: 20251219

Claims (20)

1 . A bitcell for a memory device, comprising: a left leg, the left leg comprising: one or more first magnetic tunnel junctions (MTJs); one or more first write circuitries connected to the one or more first MTJs, the one or more first write circuitries configurable to execute a write operation for the one or more first MTJs based on a write control signal; and one or more first read circuitries connected to the one or more first MTJs, the one or more first read circuitries configurable to execute a read operation for the one or more first MTJs based on a read control signal; and a right leg, the right leg comprising: one or more second magnetic tunnel junctions (MTJs); one or more second write circuitries connected to the one or more second MTJs, the one or more second write circuitries configurable to execute a write operation for the one or more second MTJs based on the write control signal; and one or more second read circuitries connected to the one or more second MTJs, the one or more second read circuitries configurable to execute a read operation for the one or more second MTJs based on the read control signal.
2 . The bitcell of claim 1 , further comprising one or more logic circuitries connected to the one or more first MTJs and the one or more second MTJs, the one or more logic circuitries configured to transmit voltage to the one or more first MTJs and the one or more second MTJs for the execution of the read operation or the write operation.
3 . The bitcell of claim 1 , wherein the one or more first read circuitries and the one or more second read circuitries comprise one or more cross coupled pairs of switching transistors, the one or more cross coupled pairs of switching transistors configured to provide positive feedback of voltage between the left leg and the right leg for the execution of the read operation.
4 . The bitcell of claim 1 , further comprising a flip-flop connected to the one or more first MTJs and the one or more second MTJs, the flip-flop configured to load a data in (din) to the one or more first MTJs and/or the one or more second MTJs based on a clock signal and the write control signal for the execution of the write operation.
5 . The bitcell of claim 1 , further comprising an output latch connected to the one or more first read circuitries and the one or more second read circuitries, the output latch configured to receive an output signal from the one or more first MTJs and/or the one or more second MTJs based on a clock signal and the read control signal for the execution of the read operation.
6 . The bitcell of claim 1 , wherein the execution of the read operation comprises: comparing a logic state of the one or more first MTJs to a logic state of the one or more second MTJs to detect a difference in resistance between the one or more first MTJs and the one or more second MTJs as part of a differential read scheme; and detecting one or more stored bits in the one or more first MTJs and/or the one or more second MTJs based on the comparison.
7 . The bitcell of claim 1 , further comprising: a pair of follower transistors connected to the one or more first MTJs and the one or more second MTJs, the pair of follower transistors configured to control a voltage level across the one or more first MTJs and/or the one or more second MTJs for the execution of the read operation.
8 . The bitcell of claim 1 , further comprising: a pair of follower transistors connected to the one or more first MTJs and the one or more second MTJs, wherein the pair of follower transistors include N-Channel Metal-Oxide-Semiconductor (NMOS) transistors or P-Channel Metal-Oxide-Semiconductor (PMOS) transistors.
9 . A bitcell for a memory device, comprising: a first leg including: one or more first magnetoresistive devices; one or more first write circuitries connected to the one or more first magnetoresistive devices, the one or more first write circuitries configurable to execute a write operation for the one or more first magnetoresistive devices based on a write control signal and a first clock signal; and one or more first read circuitries connected to the one or more first magnetoresistive devices, the one or more first read circuitries configurable to execute a read operation for the one or more first magnetoresistive devices based on a read control signal and a second clock signal; and a second leg including: one or more second magnetoresistive devices; one or more second write circuitries connected to the one or more second magnetoresistive devices, the one or more second write circuitries configurable to execute a write operation for the one or more second magnetoresistive devices based on the write control signal and the first clock signal; and one or more second read circuitries connected to the one or more second magnetoresistive devices, the one or more second read circuitries configurable to execute a read operation for the one or more second magnetoresistive devices based on the read control signal and the second clock signal.
10 . The bitcell of claim 9 , further comprising one or more logic circuitries connected to the one or more first magnetoresistive devices and the one or more second magnetoresistive devices, the one or more logic circuitries configured to transmit voltage to the one or more first magnetoresistive devices and the one or more second magnetoresistive devices for the execution of the read operation or the write operation.
11 . The bitcell of claim 9 , wherein the one or more first read circuitries and the one or more second read circuitries comprise one or more cross coupled pairs of switching transistors, the one or more cross coupled pairs of switching transistors configured to provide positive feedback of voltage between the first leg and the second leg for the execution of the read operation.
12 . The bitcell of claim 9 , further comprising a flip-flop connected to the one or more first magnetoresistive devices and the one or more second magnetoresistive devices, the flip-flop configured to load a data in (din) to the one or more first magnetoresistive devices and/or the one or more second magnetoresistive devices based on a clock signal and the write control signal for the execution of the write operation.
13 . The bitcell of claim 9 , further comprising an output latch connected to the one or more first read circuitries and the one or more second read circuitries, the output latch configured to receive an output signal from the one or more first magnetoresistive devices and/or the one or more second magnetoresistive devices based on a clock signal and the read control signal for the execution of the read operation.
14 . The bitcell of claim 9 , wherein the execution of the read operation comprises: comparing a logic state of the one or more first magnetoresistive devices to a logic state of the one or more second magnetoresistive devices to detect a difference in resistance between the one or more first magnetoresistive devices and the one or more second magnetoresistive devices as part of a differential read scheme; and detecting one or more stored bits in the one or more first magnetoresistive devices and/or the one or more second magnetoresistive devices based on the comparison.
15 . The bitcell of claim 9 , further comprising: a pair of follower transistors connected to the one or more first magnetoresistive devices and the one or more second magnetoresistive devices, the pair of follower transistors configured to control a voltage level across the one or more first magnetoresistive devices and/or the one or more second magnetoresistive devices for the execution of the read operation.
16 . The bitcell of claim 9 , further comprising: a pair of follower transistors connected to the one or more first magnetoresistive devices and the one or more second magnetoresistive devices, wherein the pair of follower transistors include N-Channel Metal-Oxide-Semiconductor (NMOS) transistors or P-Channel Metal-Oxide-Semiconductor (PMOS) transistors.
17 . The bitcell of claim 9 , wherein one or more first magnetoresistive devices include one or more magnetic tunnel junctions (MTJs).
18 . The bitcell of claim 9 , wherein the first clock signal includes a first phase and the second clock signal includes a second phase.
19 . The bitcell of claim 9 , wherein the first clock signal includes a first phase and the second clock signal includes a second phase and the first phase is different than the second phase.
20 . A bitcell for a memory device, comprising: a first leg including: one or more first magnetic tunnel junctions (MTJs); one or more first write circuitries connected to the one or more first MTJs, the one or more first write circuitries configurable to execute a write operation for the one or more first MTJs and optionally configurable to be grounded; and one or more first read circuitries connected to the one or more first MTJs, the one or more first read circuitries configurable to execute a read operation for the one or more first MTJs based at least on a first clock signal; and a second leg including: one or more second magnetic tunnel junctions (MTJs); one or more second write circuitries connected to the one or more second MTJs, the one or more second write circuitries configurable to execute a write operation for the one or more second MTJs and optionally configurable to be grounded; and one or more second read circuitries connected to the one or more second MTJs, the one or more second read circuitries configurable to execute a read operation for the one or more second MTJs based at least on a second clock signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. patent application Ser. No. 18/478,643, filed Sep. 29, 2023, which claims benefit to U.S. Provisional Ser. No. 63/378,201, filed Oct. 3, 2022, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD Various embodiments of the present disclosure relate generally to storage devices and, more particularly, to scan chain circuitry including non-volatile distributed storage bits using a shared control signal for execution of one or more operations. INTRODUCTION In general, a memory system may include a memory device for storing data and a host (or controller) for controlling operations of the memory device. Memory devices may be classified into volatile memory (such as, e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM), etc.) and non-volatile memory (such as, e.g., electrically erasable programmable read-only memory (EEPROM), ferroelectric random-access memory (FRAM), phase-change memory (PRAM), magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM/ReRAM), flash memory, etc.). Storage bits in non-volatile memories, when distributed in a distributed manner (e.g., non-volatile distributed storage bits), may provide a number of benefits for usage in field programmable gate array (FPGA) configuration storages, neural network weights/bias storages, physically unclonable function (PUF) implementations, and the like. Memory operations (e.g., read, write, etc.) performed in such architectures may require propagation of various control signals (e.g., read control signal, write control signal, etc.) to the distributed storage bits via corresponding read/write circuitries. Specifically, each non-volatile distributed storage bit may need individual routing of control signals for operation. As the number of non-volatile distributed storage bits that need to be implemented increases, routing individual control signals to each storage bit may become challenging. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and together with the description, serve to explain the principles of the disclosed embodiments. FIG. 1 depicts an exemplary block diagram of a plurality of non-volatile distributed storage bits (nvbits) implemented in a memory device, according to one or more embodiments. FIG. 2 depicts an exemplary block diagram of a plurality of nvbits implemented in a scan chain circuitry for a memory device, according to one or more embodiments. FIG. 3 depicts an exemplary circuit schematic of a bitcell for implementing an nvbit in a memory device, according to one or more embodiments. FIG. 4 depicts an exemplary circuit schematic of a bitcell for implementing an nvbit in a memory device using a pair of follower transistors, according to one or more embodiments. FIG. 5 depicts an exemplary block diagram of a scan chain circuitry implemented with one or more nvbits, according to one or more embodiments. FIG. 6 depicts an exemplary circuit schematic of a bitcell for implementing an nvbit in a memory device using a scan chain circuitry, according to one or more embodiments. FIG. 7 depicts an exemplary layout of a memory device for implementing an nvbit bitcell with dummy magnetic tunnel junctions (MTJs), according to one or more embodiments. FIG. 8 depicts an exemplary layout of a memory device for implementing a plurality of nvbit bitcells with dummy MTJs, according to one or more embodiments. DETAILED DESCRIPTION OF EMBODIMENTS Detailed illustrative aspects are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present disclosure. The present disclosure may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein. Further, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments described herein. When the specification makes reference to “one embodiment” or to “an embodiment,” it is intended to mean that a particular feature, structure, characteristic, or function described in connection with the embodiment being discussed is included in at least one contemplated embodiment of the present disclosure. Thus, the appearance of the phrases, “in one embodiment” or “in an embodiment,” in different places in the specification does not constitute a plurality of references to a single embodiment of the present disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It also should be noted that in some alternative implementations, the features and/or steps described may occur out of the or