US-20260128074-A1 - CAPACITORLESS MEMORY CELL AND MEMORY DEVICE COMPRISING THE SAME

US20260128074A1US 20260128074 A1US20260128074 A1US 20260128074A1US-20260128074-A1

Abstract

The present disclosure provides a capacitorless semiconductor memory device including a plurality of a semiconductor memory cell arrays comprising a plurality of semiconductor memory cells including a write transistor and a read transistor, the read transistor including a drain region, a control electrode, and a source region; a diode connected to the source region of the read transistor; and a sensing amplifier in connection with a read bit line, wherein the semiconductor memory device has a capacitorless structure that does not include a storage capacitor.

Inventors

Cheol Seong Hwang

Assignees

SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Dates

Publication Date: 20260507
Application Date: 20251103
Priority Date: 20241105

Claims (20)

1 . A semiconductor memory device, comprising: a plurality of a semiconductor memory cell arrays comprising a plurality of semiconductor memory cells including a write transistor and a read transistor, the read transistor including a drain region, a control electrode, and a source region; a diode connected to the source region of the read transistor; and a sensing amplifier in connection with a read bit line, wherein the semiconductor memory device has a capacitorless structure that does not include a storage capacitor.
2 . The device of claim 1 , wherein leakage current from a read word line to the read bit line is blocked by the diode when an operating voltage value (V dd ) is applied to a non-selective semiconductor memory cell among the semiconductor memory cells included in the semiconductor memory cell arrays.
3 . The device of claim 1 , further comprising: a clamping circuit in parallel connection with the sensing amplifier, wherein the clamping circuit causes a minimum value of a voltage on the read bit line to be a clamping voltage value.
4 . The device of claim 1 , when the read bit line voltage of a non-selected semiconductor memory cell of the semiconductor memory cell is set to 0V and the read word line voltage is set to an operating voltage value (V dd ), wherein a voltage value between a drain region and a source region of the non-selected semiconductor memory cell is a value of the operating voltage value (V dd ) minus a diode voltage value (V diode ).
5 . The device of claim 4 , wherein the diode voltage value (V diode )is set below a clamping voltage value (V cl ) provided by the clamping circuit.
6 . A semiconductor memory device, comprising: a plurality of semiconductor memory cell arrays including a first transistor and a second transistor, disposed in a cross-array structure on a substrate; a plurality of read bit line (RBL) and write bit line (WBL) pairs and a plurality of read word line (RWL) and write word line (WWL) pairs associated with the semiconductor memory cell arrays; and a read circuitry connected to the pairs of read bit lines and write bit lines to perform a read operation, wherein the first transistor includes an n-type semiconductor channel layer, a source contact in contact with a source region, and a drain contact in contact with a drain region, and is connected in series with the second transistor, and the first transistor is a read transistor, and the second transistor is a write transistor, and the source contact comprises a high work function metal to form a Schottky barrier at an interface with the n-type semiconductor channel layer, thereby blocking leakage current from the read word line to the read bit line in an unselected memory cell, and the drain contact comprises a low work function metal to facilitate the movement of electrons, and the semiconductor memory device has a capacitorless structure that does not include a storage capacitor.
7 . The device of claim 6 , wherein the first transistor comprises an IGZO channel comprising at least one of indium, gallium, zinc, and oxygen.
8 . The device of claim 6 , wherein source contact of the first transistor comprises a material having a work function of at least 4.7 eV.
9 . The device of claim 6 , wherein the source contact of the first transistor comprises Ru, Au, Pt Ni, Pt, or an alloy thereof.
10 . The device of claim 6 , wherein the drain contact of the first transistor comprises a material constituting ohmic contact.
11 . The device of claim 6 , wherein the drain contact of the first transistor comprises at least one of Ti, TiN, Al, and alloys thereof.
12 . The device of claim 6 , wherein the read transistor comprises an IGZO channel comprising at least one of indium, gallium, zinc, and oxygen, wherein the source contact comprises Pt or a Pt alloy material, and the drain contact comprises Ti or a Ti alloy material.
13 . The device of claim 6 , further comprising: a clamping circuit in parallel connection with the sensing amplifier, wherein the clamping circuitry causes a minimum value of a voltage on the read bit line to be a clamping voltage value.
14 . A semiconductor memory device, comprising: a plurality of semiconductor memory cell arrays including a first transistor and a second transistor, disposed in a cross-array structure on a substrate; a plurality of read bit line (RBL) and write bit line (WBL) pairs and a plurality of read word line (RWL) and write word line (WWL) pairs associated with the semiconductor memory cell arrays; and a read circuitry connected to the pairs of read bit lines and write bit lines to perform a read operation, wherein the first transistor includes a p-type semiconductor channel layer, a source contact contacting a source region, and a drain contact contacting a drain region, and is connected in series with the second transistor, and the source contact comprises a low work function metal to increase a hole injection barrier at the interface with the p-type semiconductor channel layer to block leakage current from the read word line to the read bit line in an unselected memory cell, and the drain contact comprises a high work function metal to facilitate hole injection, and the semiconductor memory device has a capacitorless structure that does not include a storage capacitor.
15 . The device of claim 14 , wherein the low work function metal comprises aluminum, titanium, silver, or a combination thereof.
16 . The device of claim 14 , wherein the high work function metal comprises platinum, ruthenium, palladium, or combinations thereof.
17 . The device of claim 14 , wherein the first transistor comprises a p-type oxide semiconductor channel layer.
18 . The device of claim 14 , wherein a storage node in a path in which the first transistor and the second transistor are connected in series stores a charge.
19 . The device of claim 14 , wherein the first transistor is a read transistor, and the second transistor is a write transistor.
20 . The device of claim 14 , wherein a read margin of the entire semiconductor memory cell arrays is formed by suppression of the leakage current.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority of Korean Patent Application No. 10-2024-0155482, filed on November 5, 2024, and priority of Korean Patent Application No. 10-2025-0154425, filed on October 23, 2025, in the KIPO (Korean Intellectual Property Office), the disclosure of which is incorporated herein entirely by reference. BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory device technology, and more particularly to a capacitorless memory cell and a memory device comprising the same. Description of the Related Art Today, dynamic random access memory (DRAM), a semiconductor memory that randomly writes and reads data at high speed, is widely used in data storage devices or devices. DRAM includes a plurality of repeated memory cells, each of which typically includes a capacitor configured to store data information and a transistor configured to control the reading of data information from the capacitor structure. To facilitate the integrated development of such memory cells, a related art has developed techniques for using memory cells in a 2T0C structure. The 2T0C structure uses two transistors as memory elements and does not include a capacitor, which reduces the volume occupied by the memory cell. In addition, neighboring memory cells may be organized by sharing word lines and bit lines. However, these 2T0C DRAMs may suffer from interference when reading a selected cell depending on the state of neighboring cells that share word lines and bit lines. For example, if the selected cell is off (data 0) and the three neighboring cells are all on (data 1), the selected cell has a higher probability of being interfered with by the three neighboring cells. Therefore, there is a great need to develop a 2TOC circuit that may solve the problem of interference between neighboring memory cells. In particular, since DRAM may be used not only as a memory but also as a neuromorphic device for artificial intelligence, according to today's technology trends, it is necessary to develop a 2T0C circuit that may be used without interference from neighboring cells and without data reading errors. SUMMARY OF THE INVENTION The technical challenge of the present invention is to provide an asymmetric electrode structure and memory cells that may be used in memory requiring error-free and accurate operation as well as neuromorphic devices for artificial intelligence by preventing leakage currents between neighboring cells to read selected cells without interference from neighboring cells. Furthermore, by implementing a capacitorless structure that does not include a capacitor, it is possible to provide a capacitorless memory device that is advantageous for high integration and improves the reading margin by reducing inter-cell interference. A capacitorless semiconductor memory device according to one embodiment of the present invention includes a plurality of memory cells comprising write transistors and read transistors, the read transistors comprising a memory cell array including a drain region, a control electrode, and a source region; a diode connected to the source region of the read transistors; and a sensing amplifier connected to the read bit line. Leakage current from the read word line to the read bit line is blocked by the diode when an operating voltage value (Vdd)is applied to a non-selective memory cell among the memory cells included in the memory cell array. Further, the capacitorless semiconductor memory device further comprises a clamping circuit connected in parallel with the sensing amplifier, the clamping circuit causing a minimum value of the voltage on the read bit line to be a clamping voltage value. Further, when the read bit line voltage of a non-selected memory cell of the memory cell is set to 0V and the read word line voltage is set to an operating voltage value (Vdd), a voltage value between a drain region and a source region of the non-selected memory cell may be a value of the operating voltage value (Vdd)minus a diode voltage value (Vdiode). Further, a capacitorless semiconductor memory device according to another embodiment of the present invention includes a memory cell array comprising a plurality of memory cells including a write transistor and a read transistor; a bit line connected with a source region of the read transistor; and a sensing amplifier connected with the bit line, wherein the contact material of the source region of the read transistor comprises a Schottky contact material. The read transistor includes an IGZO channel comprising at least one of indium, gallium, zinc, and oxygen. Further, the source contact of the read transistor may include a material having a work function of at least 4.7 eV. Further, the source contact of the read transistor may include Ru, Au, Pd, Ni, Pt, or an alloy thereof. Further, the drain contact of the read transistor may be a material constituting an ohmic contact. F