US-20260128075-A1 - MEMORY DEVICE PERFORMING REFRESH OPERATION BASED ON RANDOM VALUE AND METHOD OF OPERATING SAME

Abstract

A memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.

Inventors

• Dongha Kim
• Hyunki Kim
• Hoyoung SONG

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251230

Claims (20)

1. 1 . A memory device comprising: a memory cell array including a set of memory cells coupled to a plurality of word-lines; a random bit generator configured to generate a random binary code having a predetermined number of bits; and a refresh controller configured to: generate a set of sampling addresses by sampling addresses associated with access requests from a memory controller in response to the random binary code matching a reference binary code; select a first address among the set of sampling addresses; and in response to receiving a refresh command from the memory controller; refresh first subset of memory cells among the set of memory cells based on the first address.
2. 2 . The memory device of claim 1 , wherein the memory device is configured to receive an active command, and wherein the random bit generator is configured to output the random binary code in response to the active command received from the memory controller.
3. 3 . The memory device of claim 1 , wherein the random bit generator is configured to generate the random binary code based on a pseudo random sequence.
4. 4 . The memory device of claim 1 , wherein the refresh command corresponds to an N-th refresh command among N refresh commands received from the memory controller and N is an integer greater than one.
5. 5 . The memory device of claim 1 , wherein the refresh controller is configured to refresh the first subset of memory cells by generating a refresh control signal for refreshing the first subset of memory cells based on the refresh command.
6. 6 . The memory device of claim 1 , wherein the first address corresponds to a sampling address that was accessed the most often among the set of sampling addresses.
7. 7 . The memory device of claim 6 , wherein the refresh control controller comprises: refresh registers configured to store the set of sampling addresses, wherein the refresh controller is configured to determine a sampling address stored in a refresh register corresponding to a maximum counting value among the refresh registers as the first address.
8. 8 . The memory device of claim 6 , wherein the first subset of memory cells is associated with a second word-line adjacent to a first word-line among the plurality of word-lines, the first word-line being associated with the first address.
9. 9 . The memory device of claim 1 , further comprising: a comparator configured to: compare the random binary code and the reference binary code; and generate a matching signal indicating that the random binary code matches the reference binary code.
10. 10 . The memory device of claim 9 , wherein the refresh controller is further configured to generate the set of sampling addresses in response to the matching signal generated by the comparator.
11. 11 . A method of operating a memory device including a set of memory cells coupled to a set of word-lines, the method comprising: generating a set of sampling address by sampling addresses associated with access requests received from a memory controller in response to a random binary code matching a reference binary code; terminate the generating of the set of sampling address in response to receiving a refresh command from the memory controller; and refreshing a first subset of memory cells among the set of memory cells based on a first address selected from the set of sampling addresses in response to the refresh command.
12. 12 . The method of claim 11 , further comprising receiving an active command, wherein the random binary code is generated in response to an active command received from the memory controller.
13. 13 . The method of claim 11 , wherein the random binary code is generated based on a pseudo random sequence.
14. 14 . The method of claim 11 , further comprising: comparing the random binary code and the reference binary code; and generating a matching signal indicating that the random binary code matches the reference binary code.
15. 15 . The method of claim 14 , wherein the generating the set of sampling is initiated based on the generation of the matching signal.
16. 16 . The method of claim 11 , wherein the first address selected from the set of sampling addresses corresponds to a sampling address that was accessed the most often among the set of sampling addresses, and wherein the first subset of memory cells is associated with a second word-line adjacent to a first word-line among the plurality of word-lines, the first word-line being associated with the first address.
17. 17 . A memory device comprising: a memory cell array including a set of memory cells coupled to a set of word-lines; a random bit generator configured to generate a random binary code having a predetermined number of bits; a comparator configured to compare the random binary code and a reference binary code; and a refresh controller configured to select a selected sampling address of a set of sampling addresses accessed by a memory controller during a sampling period to refresh a first subset of memory cells among the set of memory cells based on the selected sampling address, the sampling period randomly determined based on a result of the comparison of the random binary code and the reference binary code.
18. 18 . The memory device of claim 17 , wherein the refresh controller is configured to determine a maximum access address, which is mostly accessed, among the addresses accessed during the sampling period and configured to generate a refresh address corresponding to the first subset of memory cells based on the maximum access address.
19. 19 . The memory device of claim 18 , wherein the maximum access address designates a first word-line among the set of word-lines and the refresh address designates at least a second word-line adjacent to the first word-line, among the set of word-lines.
20. 20 . The memory device of claim 17 , wherein the sampling period is determined as a time period between a time point at which the comparator outputs the matching signal indicating that the random binary code matches the reference binary code and a time point at which the refresh controller receives the refresh command.

Description

TECHNICAL FIELD This application is a Continuation of U.S. Patent Application No. 18/170,420, filed on February 16, 2023, which is a Continuation of U.S. Patent Application No. 17/244,261 filed April 29, 2021. Example embodiments relate to memory devices, and more particularly, to memory devices performing refresh operation and methods of operating the same. DISCUSSION OF RELATED ART A dynamic random access memory (DRAM) device may store data by storing a charge to a capacitor of a memory cell connected to a given word-line. The DRAM device may periodically refresh the memory cell since charges in the capacitor leak over time. The influence of charges of an adjacent memory cell connected to another word-line adjacent to the given word-line increases as processes for manufacturing memory devices are scaled down and periods between word-lines become narrower. When the given word-line (e.g., the active state word-line) is intensively accessed, a row hammer may occur in an adjacent memory cell. That is, due to a voltage of the active state word-line, data stored in the memory cells connected to other word-lines adjacent to the active state word-line may be lost or changed to an unintended state. SUMMARY At least one exemplary embodiment of the inventive concept provides a memory device capable of preventing data from being lost due to a specified word-line being intensively accessed. At least one exemplary embodiment of the inventive concept provides a method of operating a memory device, capable of preventing data from being lost due to a specified word-line being intensively accessed. According to an exemplary embodiment of the inventive concept, a memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller. According to an exemplary embodiment of the inventive concept, a memory device includes a memory cell array, a control logic circuit and a row decoder. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The control logic circuit generates a refresh address based on first sampling addresses accessed by a memory controller during a first sampling period and second sampling addresses accessed by the memory controller during a second sampling period. The row decoder refreshes target memory cells corresponding to the refresh address, from among the plurality of memory cells. The first sampling period is determined based on a first refresh command from the memory controller and a first matching signal that is randomly generated. The second sampling period is determined based on a second refresh command from the memory controller and a second matching signal that is randomly generated. According to an exemplary embodiment of the inventive concept, a method of operating a memory device including a plurality of memory cells coupled to a plurality of word-lines is provided. The method includes sampling addresses provided from a memory controller in response to a first refresh command to generate first sample addresses; halting an operation to sample the addresses provided from the memory controller in response to a first matching signal randomly generated after receiving the first refresh command; refreshing first memory cells from among the plurality of memory cells based on a second refresh command and one of the first sample addresses to sample addresses provided from the memory controller after the first matching signal being generated to generate second sample addresses; halting an operation to sample the addresses provided from the memory controller in response to a second matching signal randomly generated after receiving the second refresh command; and refreshing second memory cells from among the plurality of memory cells based on a third refresh command and one of the first sample addresses and the second sample addresses. The third refresh command is provided from the memory controller after the second matching signal being generated. According to an exemplary embodiment of the inventive concept, a memory device includes a memory cell array, a random number generator, and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random number generator is configured to generate a random number. The refresh controller is configured to begin sampling addresses of