US-20260128076-A1 - ROW HAMMER MITIGATION

Abstract

A 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate. Counter and counter control circuits for each row in the memory cell array are fabricated under the array. These counters track the number of row hammers each row experiences. When a counter indicates a row has experienced a threshold number of row hammers, that row is refreshed. The row may be refreshed immediately after the current row is closed. The row may be scheduled to be refreshed as part of a regular refresh sequence. A signal may be sent to the memory controlling indicating that the bank with the row being refreshed immediately should not be accessed until the refresh is complete.

Inventors

• Thomas Vogelsang
• Torsten Partsch

Assignees

• RAMBUS INC.

Dates

Publication Date

20260507

Application Date

20250909

Claims (20)

1. 1 . (canceled)
2. 2 . A controller, comprising: an interface to communicate with a memory device where the memory device comprises an array of memory cells having a plurality of rows; and control circuitry to: based on receiving, from the memory device, an indicator that the memory device is performing a refresh of a row of the array of memory cells based on a counter value corresponding to the row of the array of memory cells meeting a row-hammer threshold, where the memory device performs the refresh without an intervening operation on the array of memory cells after another row of the array of memory cells is closed; and in response to the indicator, inhibit accesses to a bank of the memory device that include the row until the refresh is complete.
3. 3 . The controller of claim 2 , wherein the indicator is transmitted in response to the counter value corresponding to the row meeting the row-hammer threshold.
4. 4 . The controller of claim 2 , wherein the memory device comprises a plurality of counters disposed underneath the array of memory cells, wherein each of the plurality of counters correspond to a respective one of the plurality of rows.
5. 5 . The controller of claim 4 , wherein respective counters of the plurality of counters are advanced in response to activations of a neighbor rows.
6. 6 . The controller of claim 4 , wherein the controller issues commands to the memory device that cause the memory device to update one or more of the counters.
7. 7 . The controller of claim 4 , wherein an activation of a respective row causes a respective counter corresponding to the respective row to be initialized.
8. 8 . The controller of claim 4 , wherein the memory device further comprises counter threshold circuitry, disposed under the array of memory cells to compare counter values to the row-hammer threshold.
9. 9 . A controller, comprising: an interface to communicate with a memory device that includes a memory array; and control circuitry to, based on an indicator from the memory device that the memory device is performing a memory device initiated refresh operation on the memory array, inhibit memory access commands directed to the memory array until the refresh operation has completed.
10. 10 . The controller of claim 9 , wherein the memory device initiated refresh operation is performed based on a counter value meeting a row-hammer threshold.
11. 11 . The controller of claim 10 , wherein a memory device initiated refresh of a first row is based on a refresh operation being performed on a second row.
12. 12 . The controller of claim 11 , wherein the second row is physically adjacent to the first row.
13. 13 . The controller of claim 12 , wherein the refresh operation being performed on a second row causes a counter value associated with the first row to meet the row-hammer threshold.
14. 14 . The controller of claim 10 , wherein the memory device comprises a plurality of counters disposed underneath the memory array.
15. 15 . The controller of claim 14 , wherein each of the plurality of counters corresponds to a respective row of the memory array.
16. 16 . The controller of claim 15 , wherein respective ones of the plurality of counters are updated based on activations of rows that neighbor the respective ones of the plurality of counters.
17. 17 . A method of operating a controller coupled with a memory device that includes an array of memory cells comprising a plurality of rows, the method comprising: receiving, from the memory device, an indicator that the memory device is performing a memory device initiated refresh operation of a row of the plurality of rows based on a row-hammer counter value corresponding to the row meeting a row-hammer threshold; and based on receiving the indicator, inhibiting accesses of the array until the memory device initiated refresh operation is complete.
18. 18 . The method of claim 17 , wherein the memory device comprises a plurality of row-hammer counters disposed underneath the array of memory cells.
19. 19 . The method of claim 18 , wherein the memory device comprises threshold circuitry disposed underneath the array of memory cells that determines whether at least one of the row-hammer counters has a value that meets the row-hammer threshold.
20. 20 . The method of claim 19 , wherein a value in a first row-hammer counter corresponding to a first row advances based activations of a second row that is adjacent to the first row.

Description

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-section illustration of an example memory array tile (MAT) of a three-dimensional (3D) dynamic random access memory (DRAM). FIG. 1B is an example floorplan of selected layers of the example MAT of the 3D DRAM. FIG. 2 is an illustration of an example 3D DRAM chip floorplan for row hammer mitigation. FIG. 3 is a block diagram illustrating example counter and control circuitry to mitigate row hammer. FIG. 4 is a flowchart illustrating an example method of mitigating row hammer. FIG. 5 is a block diagram illustrating example circuitry to refresh rows of a bank. FIG. 6 is a timing diagram illustrating example signals to update row hammer counters and refresh a hammered row that meets the row hammer threshold count. FIG. 7 is a flowchart illustrating an example method of tracking rows being hammered. FIG. 8 is a flowchart illustrating an example method of refresh tracking. FIG. 9 is a flowchart illustrating an example method of scheduling a refresh for a row being hammered. FIG. 10 is a block diagram of a processing system. DETAILED DESCRIPTION OF THE EMBODIMENTS Repeated row activations of the same row in a memory device (e.g., dynamic random access memory—DRAM), whether malicious or accidental, may cause cells in the neighborhood of the repeatedly activated row to lose a stored value. This effect on storage reliability has been termed “row hammer.” In an embodiment, a 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate. Counter and counter control circuits for each row in the memory cell array are fabricated under the array. These counters track the number of row hammers each row experiences. In an embodiment, when a counter indicates a row has experienced a threshold number of row hammers, that row is refreshed. In an embodiment, the row may be refreshed immediately after the current row is closed. In an embodiment, the row is scheduled to be refreshed as part of a regular refresh sequence. If the row is refreshed immediately, a signal may be sent to the memory controlling indicating that the bank with the row should not be accessed until the refresh is complete. FIG. 1A is a cross-section illustration of an example three-dimensional (3D) dynamic random access memory (DRAM). FIG. 1B is an example floorplan of selected layers of the example MAT of the 3D DRAM. In FIGS. 1A-1B, memory array tile 100 is disposed on substrate 101 (e.g., silicon) and comprises transistors for counters and control circuitry 110, transistors for sense amplifier circuitry 120a-120b, lowest level interconnect (M0) layer 140 (e.g., polysilicon or metal), second lowest level interconnect (M1) layer 141 (e.g., metal), third lowest level interconnect (M2) layer 142, top level interconnect (M3) layer 143, vias 131a-131b, capacitor arrays 150a-150b, wordlines and access transistors layer 151a-151b, bitline layer 152, and sub-wordline drivers 153a-153b. In FIG. 1A, the transistors for counters and control circuitry 110 and the transistors for sense amplifier circuitry 120a-120b are illustrated as fabricated in substrate 101. The next layer above the transistors for counters and control circuitry 110 and the transistors for sense amplifier circuitry 120a-120b is the M0 interconnect layer 140. Above the M0 interconnect layer is the M1 interconnect layer 141. Above the M1 interconnect layer is capacitor array 150a. Above capacitor array 150a is wordline and access transistor layer 151a. Above the wordline and access transistor layer 151a is the bitline layer 152. Above bitline layer 152 is wordline and access transistor layer 151b. Above wordline and access transistor layer 151b is capacitor array 150b. Above capacitor array 150b is the M2 interconnect layer 142. Above the M2 interconnect layer is the M3 interconnect layer 143. Vias 131a-131b run vertically to interconnect the circuitry of wordlines and access transistor layers 151a-151b and/or bitline layer 152 to one or more of M1 layer 141 and/or M2 layer 142. Counters and control circuitry 110 comprises the transistors for counters and control circuitry 110 that are fabricated in substrate 101, at least a portion of the M0 layer 140 above the transistors for counters and control circuitry 110, and may also include at least a portion of the M1 layer 141 above the transistors for counters and control circuitry 110. Thus, it should be understood that counters and control circuitry 110 includes interconnect or other elements (e.g., polysilicon gates) formed in the M0 layer 140. Thus, the M0 layer 140 and optionally the M1 layer 141 may be used to interconnect the transistors for counters and control circuitry 110 thereby forming the active circuits of counters and control circuitry 110. This is illustrated in FIG. 1A by the dotted lines running from the left and right edges of counters and