US-20260128077-A1 - REFRESH RATE DETERMINATION USING BIT SHIFTING

US20260128077A1US 20260128077 A1US20260128077 A1US 20260128077A1US-20260128077-A1

Abstract

Methods, systems, and devices for refresh rate determination using bit shifting are described. A memory system may obtain a first temperature range of a set of temperature ranges that includes an operating temperature measured at the memory system and receive a first set of bits that indicates a base refresh rate associated with a second temperature range of the set of temperature ranges. Further, the memory system may apply a quantity of bit shifts to the first set of bits to generate a second set of bits that indicates a second refresh rate based on a difference between the first temperature range and the second temperature range. The memory system may refresh during a first duration according to the second refresh rate indicated by the second set of bits.

Inventors

Geoffrey B. Luken

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20251030

Claims (20)

1 . A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: obtain a first temperature range of a plurality of temperature ranges, wherein the first temperature range includes an operating temperature measured at the memory system; receive a first set of bits that indicates a base refresh rate associated with a second temperature range of the plurality of temperature ranges; apply a quantity of bit shifts to the first set of bits to generate a second set of bits based at least in part on a difference between the first temperature range and the second temperature range, the second set of bits indicating a second refresh rate; and refresh, during a first duration, the memory system according to the second refresh rate indicated by the second set of bits.
2 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: apply a second quantity of bit shifts to the second set of bits to generate a third set of bits that indicates a third refresh rate.
3 . The memory system of claim 2 , wherein the processing circuitry is further configured to cause the memory system to: refresh, during a second duration, the memory system according to the third refresh rate indicated by the third set of bits.
4 . The memory system of claim 1 , wherein, to apply the quantity of bit shifts to the first set of bits, the processing circuitry is configured to cause the memory system to: drop one or more bits of the first set of bits; and shift the remaining bits of the first set of bits to a less significant bit position.
5 . The memory system of claim 1 , wherein the base refresh rate is less than the second refresh rate.
6 . The memory system of claim 1 , wherein, to apply the quantity of bit shifts to the first set of bits, the processing circuitry is configured to cause the memory system to: apply one bit shift to the first set of bits based at least in part on the first temperature range being adjacent to the second temperature range.
7 . The memory system of claim 6 , wherein, to apply the one bit shift to the first set of bits, the processing circuitry is configured to cause the memory system to: divide a duration between refreshes by two to generate the second refresh rate, the duration associated with the base refresh rate.
8 . The memory system of claim 1 , wherein a quantity of temperature ranges comprising the plurality of temperature ranges is equal to a quantity of bits comprising the first set of bits.
9 . A method by a memory system, comprising: obtaining a first temperature range of a plurality of temperature ranges, wherein the first temperature range includes an operating temperature measured at the memory system; receiving a first set of bits that indicates a base refresh rate associated with a second temperature range of the plurality of temperature ranges; applying a quantity of bit shifts to the first set of bits to generate a second set of bits based at least in part on a difference between the first temperature range and the second temperature range, the second set of bits indicating a second refresh rate; and refreshing, during a first duration, the memory system according to the second refresh rate indicated by the second set of bits.
10 . The method of claim 9 , further comprising: applying a second quantity of bit shifts to the second set of bits to generate a third set of bits that indicates a third refresh rate.
11 . The method of claim 10 , further comprising: refreshing, during a second duration, the memory system according to the third refresh rate indicated by the third set of bits.
12 . The method of claim 9 , wherein applying the quantity of bit shifts to the first set of bits comprises: dropping one or more bits of the first set of bits; and shifting the remaining bits of the first set of bits to a less significant bit position.
13 . The method of claim 9 , wherein the base refresh rate is less than the second refresh rate.
14 . The method of claim 9 , wherein applying the quantity of bit shifts to the first set of bits comprises: applying one bit shift to the first set of bits based at least in part on the first temperature range being adjacent to the second temperature range.
15 . The method of claim 14 , wherein applying the one bit shift to the first set of bits comprises: dividing a duration between refreshes by two to generate the second refresh rate, the duration associated with the base refresh rate.
16 . The method of claim 9 , wherein a quantity of temperature ranges comprising the plurality of temperature ranges is equal to a quantity of bits comprising the first set of bits.
17 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: obtain a first temperature range of a plurality of temperature ranges, wherein the first temperature range includes an operating temperature measured at a memory system; receive a first set of bits that indicates a base refresh rate associated with a second temperature range of the plurality of temperature ranges; apply a quantity of bit shifts to the first set of bits to generate a second set of bits based at least in part on a difference between the first temperature range and the second temperature range, the second set of bits indicating a second refresh rate; and refresh, during a first duration, the memory system according to the second refresh rate indicated by the second set of bits.
18 . The non-transitory computer-readable medium of claim 17 , wherein the instructions are further executable by the one or more processors to: apply a second quantity of bit shifts to the second set of bits to generate a third set of bits that indicates a third refresh rate.
19 . The non-transitory computer-readable medium of claim 17 , wherein the instructions to apply the quantity of bit shifts to the first set of bits are executable by the one or more processors to: drop one or more bits of the first set of bits; and shift the remaining bits of the first set of bits to a less significant bit position.
20 . The non-transitory computer-readable medium of claim 17 , wherein the instructions to apply the quantity of bit shifts to the first set of bits are executable by the one or more processors to: apply one bit shift to the first set of bits based at least in part on the first temperature range being adjacent to the second temperature range.

Description

CROSS REFERENCE The present Application for Patent claims priority to U.S. patent application Ser. No. 63/716,582 by Luken, entitled “REFRESH RATE DETERMINATION USING BIT SHIFTING,” filed Nov. 5, 2024, which is assigned to the assignee hereof, and which is expressly incorporated by reference in its entirety herein. TECHNICAL FIELD The following relates to one or more systems for memory, including refresh rate determination using bit shifting. BACKGROUND Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored by the memory cell. To store information, a memory device may write (e.g., program, set, assign) states to the memory cells. To access stored information, a memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an example of a system that supports refresh rate determination using bit shifting in accordance with examples as disclosed herein. FIG. 2A shows an example of a bit shifting scheme that supports refresh rate determination using bit shifting in accordance with examples as disclosed herein. FIG. 2B shows an example of a graph that supports refresh rate determination using bit shifting in accordance with examples as disclosed herein. FIG. 3 shows an example of a component diagram that supports refresh rate determination using bit shifting in accordance with examples as disclosed herein. FIG. 4 shows a block diagram of a memory system that supports refresh rate determination using bit shifting in accordance with examples as disclosed herein. FIG. 5 shows a flowchart illustrating a method or methods that support refresh rate determination using bit shifting in accordance with examples as disclosed herein. DETAILED DESCRIPTION A memory system may perform a self-refresh operation. In some examples, the memory system may determine a frequency at which to perform the self-refresh operation based on an operating temperature of the memory system. Using other methods, the memory system may be configured with one or more refresh rate curves. Each refresh rate curve may indicate a relationship between a set of temperatures and a set of refresh rates. In some examples, the memory system may determine an operating temperature of the memory system and identify two temperatures of the set of temperatures that the operating temperature falls between (or temperature trip points). Further, the memory system may select a refresh rate curve from the one or more refresh rate curves and utilize the selected refresh rate curve to obtain a respective refresh rate for each of the identified temperatures. The memory system may then estimate (or interpolate) a refresh rate corresponding to the operating temperature using refresh rates of the temperature trip points and refresh the memory system according to the estimated refresh rate. However, this method may not offer refresh rate flexibility. That is, the memory system may be unable to change the relationship between the set of refresh rates and the set of temperatures because the set of refresh rates are set with metal switches (e.g., hardcoded using read-only memory). Thus, as performance of the memory system changes, the relationship between the set of refresh rates and the set of temperatures may stay constant resulting in an inefficient system. Further, to implement this method, the memory system may include multiple pre-configured tables (e.g., the refresh rate curves) and multiple multiplexers which may consume valuable space in the memory system. As described herein, the memory system may utilize bit shifting techniques to determine the frequency at which to perform the self-refresh operation. In some examples, the memory system may determine a refresh rate based on a base refresh rate and bit shifting scheme. A base refresh rate may be associated with a base temperature of a set of temperature ranges. If the operating temperature falls in a different temperature range than the base temperature range, then a bit shifting scheme may alter the base refresh rate indicator to determine the updated refresh rate. In this way, refresh rates may be determined algorithmically and the refresh rates may be adjusted by adjusting the base refresh rate. In some examples, the memory system may determine an operating temperature and obtain a first temperature range of a set of temperature ranges that includes the operating temperature. Further, the memory system may receive a first set of bits that indicates a base refresh rate associated with a second temperature range (e.g.,