US-20260128078-A1 - SEMICONDUCTOR DEVICE HAVING INPUT BUFFER CIRCUIT

US20260128078A1US 20260128078 A1US20260128078 A1US 20260128078A1US-20260128078-A1

Abstract

An example apparatus includes: a differential amplifier circuit having a pair of first and second input transistors, the first input transistor having a control electrode supplied with an input signal, the second input transistor having a control electrode supplied with a reference potential; and a replica circuit having first, second, and third replica transistors coupled in series. The differential amplifier circuit is configured to be activated responsive to a first timing signal. The first and second input transistors and the first and second replica transistors have a first conductivity type. The third replica transistor has a second conductivity type opposite. Each of the first and third replica transistors has a control electrode supplied with the second timing signal. The second replica transistor has a control electrode supplied with the reference potential.

Inventors

Shun NISHIMURA

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20250925

Claims (20)

1 . An apparatus comprising: an input buffer circuit; and a first replica circuit configured to replicate the input buffer circuit, wherein the input buffer circuit includes: a first transistor coupled between a first power line supplied with a first power potential and a common source line and having a control electrode supplied with a first timing signal; a second transistor coupled between the common source line and a first circuit node and having a control electrode supplied with an input signal; a third transistor coupled between the common source line and a second circuit node and having a control electrode supplied with a reference potential; and an amplifier circuit having a pair of first and second input nodes, the first input node being coupled to the first circuit node, the second input node being coupled to the second circuit node, wherein the first replica circuit includes fourth and fifth transistors coupled in series between the first power line and a third circuit node, wherein the fourth transistor has a control electrode supplied with a second timing signal, and wherein the fifth transistor has a control electrode supplied with the reference potential.
2 . The apparatus of claim 1 , wherein each of the first, second, third, fourth, and fifth transistors has a first conductivity type.
3 . The apparatus of claim 2 , wherein the first replica circuit further includes a sixth transistor coupled between the third circuit node and a second power line supplied with a second power potential different from the first power potential, and wherein the sixth transistor has a control electrode supplied with the second timing signal.
4 . The apparatus of claim 3 , wherein the sixth transistor has a second conductivity type different from the first conductivity type.
5 . The apparatus of claim 4 , wherein the fifth transistor is coupled between the fourth transistor and the sixth transistor.
6 . The apparatus of claim 5 , wherein the third circuit node is a connection node between the fifth transistor and the sixth transistor.
7 . The apparatus of claim 6 , wherein the first replica circuit further includes a seventh transistor having the first conductivity type and coupled between the first power line and the fourth transistor and an eighth transistor having the second conductivity type and coupled between the sixth transistor and the second power line, wherein the eighth transistor has a control electrode supplied with an enable signal, and wherein the seventh transistor has a control electrode supplied with an inverted signal of the enable signal.
8 . The apparatus of claim 7 , wherein the first replica circuit further includes a gate circuit configured to generate a third timing signal based on a potential of the third circuit node when the enable signal is activated.
9 . The apparatus of claim 8 , further comprising: a timing signal generator configured to generate the first timing signal based on an original timing signal supplied to an external terminal electrode; and a second replica circuit configured to replicate the timing signal generator, wherein the second replica circuit is configured to generate the second timing signal based on the third timing signal.
10 . The apparatus of claim 9 , further comprising a counter circuit configured to update a count value each time the third timing signal is activated.
11 . The apparatus of claim 6 , wherein the amplifier circuit includes a seventh transistor having a control electrode as the first input node and an eighth transistor having a control electrode as the second input node.
12 . An apparatus comprising: a timing signal generator configured to generate a first timing signal based on an original timing signal supplied from outside; a first input buffer circuit configured to latch an input data supplied from outside responsive to the first timing signal; a first replica circuit configured to generate a second timing signal based on a third timing signal; and a second replica circuit configured to generate the third timing signal based on the second timing signal, wherein the first input buffer circuit includes: first and second transistors coupled in series between a first power line supplied with a first power potential and a first circuit node; and an amplifier circuit coupled in series between the first power line and a second power line supplied with a second power potential different from the first power potential and having a first input node coupled to the first circuit node, wherein the first transistor is configured to be controlled by the first timing signal, wherein the second transistor is configured to be controlled by the input data, wherein the second replica circuit includes third, fourth, and fifth transistors coupled in series between the first and second power lines, wherein each of the first, second, third, and fourth transistors has a first conductivity type, wherein the fifth transistor has a second conductivity type different from the first conductivity type, wherein the third and fifth transistors are configured to be controlled by the second timing signal, and wherein the fourth transistor is configured to be controlled by a reference potential.
13 . The apparatus of claim 12 , wherein a potential of the input data is changed in a range of a first potential to a second potential, and wherein the reference potential is higher than the first potential and lower than the second potential.
14 . The apparatus of claim 13 , wherein the first input buffer circuit further includes a sixth transistor having the first conductivity type, wherein the first and sixth transistors are coupled in series between the first power line and a second circuit node, wherein the amplifier circuit further has a second input node coupled to the second circuit node, and wherein the sixth transistor is configured to be controlled by the reference potential.
15 . The apparatus of claim 13 , further comprising a counter circuit configured to update a count value each time the third timing signal is activated.
16 . The apparatus of claim 13 , wherein the timing signal generator includes a second input buffer circuit configured to generate a fourth timing signal based on the original timing signal, and wherein the first replica circuit includes a replica buffer circuit of the second input buffer circuit configured to generate a fifth timing signal based on the third timing signal.
17 . The apparatus of claim 16 , wherein the timing signal generator further includes a driver circuit configured to generate a sixth timing signal based on the fourth timing signal, and wherein the first replica circuit further includes a replica gating circuit of the driver circuit configured to generate a seventh timing signal based on the fifth timing signal.
18 . The apparatus of claim 17 , wherein the timing signal generator further includes a divider circuit configured to generate the first timing signal based on the sixth timing signal, and wherein the first replica circuit further includes a replica divider circuit of the divider circuit configured to generate the second timing signal based on the seventh timing signal.
19 . An apparatus comprising: a differential amplifier circuit having a pair of first and second input transistors, the first input transistor having a control electrode supplied with an input signal, the second input transistor having a control electrode supplied with a reference potential; and a replica circuit having first, second, and third replica transistors coupled in series, wherein the differential amplifier circuit is configured to be activated responsive to a first timing signal, wherein each of the first and second input transistors and the first and second replica transistors has a first conductivity type, wherein the third replica transistor has a second conductivity type different from the first conductivity type, wherein each of the first and third replica transistors has a control electrode supplied with the second timing signal, and wherein the second replica transistor has a control electrode supplied with the reference potential.
20 . The apparatus of claim 19 , further comprising a gate circuit configured to generate a third timing signal based on a potential of a circuit node between the second and third replica transistors, wherein the replica circuit and the gate circuit are configured to be activated responsive to an enable signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the filing benefit of U.S. Provisional Application No. 63/715,226, filed Nov. 1, 2024. This application is incorporated by reference herein in its entirety and for all purposes. BACKGROUND Semiconductor devices such as a DRAM may have a write oscillator circuit that monitors the time period from when a data strobe signal is input from the outside until the write data is latched in the input buffer circuit. It is desirable that the time period measured using the write oscillator circuit reflects as accurately as possible the time from when a data strobe signal is actually input from the outside until the write data is actually latched in the input buffer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present disclosure; FIG. 2 is a block diagram showing a configuration of main components of a data control circuit; FIG. 3 is a circuit diagram of a data latch circuit; FIG. 4 is a block diagram showing a configuration of a write oscillator circuit. FIG. 5 is a circuit diagram of a DQIB replica circuit; and FIG. 6 is a timing diagram for explaining the function of the write oscillator circuit. DETAILED DESCRIPTION Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments. FIG. 1 is a block diagram showing a configuration of a semiconductor memory device 10 according to an embodiment of the present disclosure. The semiconductor memory device 10 shown in FIG. 1 is an LPDDR5 DRAM and includes a memory cell array 11. When access is made to the memory cell array 11, a command address signal CA is input to a command address terminal 12 from outside. The command address signal CA is supplied to an access control circuit 13. The access control circuit 13 synchronizes with complementary clock signals CKT and CKC respectively input to clock terminals 14 and 15, thereby decoding the command address signal CA, counting latencies, and the like. When a command included in the command address signal CA indicates a read operation, the access control circuit 13 makes read-access to a memory cell included in the memory cell array 11 based on an address included in the command address signal CA. Read data DQ read from the accessed memory cell is output to outside from a data I/O terminal 17 via a data control circuit 16. When the command included in the command address signal CA indicates a write operation, write data DQ input to the data I/O terminal 17 is transferred to the memory cell array 11 via an input buffer circuit 20 included in the data control circuit 16. The write data DQ is input to the memory cell array 11 as it synchronizes with complementary data strobe signals DQST and DQSC respectively supplied to data strobe terminals 18 and 19. The write data DQ having been transferred to the memory cell array 11 is written in the memory cell included in the memory cell array 11 based on the address included in the command address signal CA. FIG. 2 is a block diagram showing a configuration of main components of the data control circuit 16. As shown in FIG. 2, the data control circuit 16 includes a gating circuit 22 that receives data strobe signals DQST and DQSC via an input buffer 21. The data strobe signals DQST and DQSC buffered by the input buffer 21 constitute a timing signal T4. Internal data strobe signals DS and DSF output from the gating circuit 22 respectively correspond to the data strobe signals DQST and DQSC. The internal data strobe signals DS and DSF constitute the timing signal T6. The internal data strobe signals DS and DSF are input to a dividing circuit 23. The dividing circuit 23 generates four-phase internal data strobe signals DQS0, DQS90, DQS180, and DQS270 by dividing the internal data strobe signals DS and DSF. When the phase of the internal data strobe signal DQS0 is 0°, the phases of the internal data strobe signals DQS90, DQS180, and DQS270 are 90°, 180°, and 270°, respectively. The internal data strobe signals DQS0, DQS90, DQS180, and DQS270 are supplied to the input buffer 20. The input buffer 20 includes a data latch circuit 200 that synchronizes with the internal data strobe signal DQS0 to latch the write