US-20260128079-A1 - MEMORY DEVICE, OPERATION METHOD, AND MEMORY SYSTEM

Abstract

Examples of the present application disclose a memory device, an operation method, and a memory system. The memory device includes: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; and a clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device.

Inventors

• Yong Fu
• Shiyang Yang
• Ling Ding

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20251231

Priority Date

20231116

Claims (20)

1. 1 . A memory device, comprising: a bias generation circuit configured to receive a bias control signal and output a target bias signal based on the bias control signal, wherein different bias control signals corresponds to different data transfer rates of the memory device; and a clock buffer circuit coupled with the bias generation circuit and configured to receive the target bias signal and adjust a working current of the clock buffer circuit based on the target bias signal.
2. 2 . The memory device of claim 1 , further comprising a control circuit coupled with the bias generation circuit and configured to: receive a configuration code to characterize the data transfer rate; and output the bias control signal to the bias generation circuit.
3. 3 . The memory device of claim 2 , wherein the control circuit comprises: a storage circuit configured to store the configuration code; and a decoding circuit coupled with the storage circuit and configured to receive the configuration code, and output the bias control signal.
4. 4 . The memory device of claim 2 , wherein the target bias signal comprises a bias current signal, and wherein the clock buffer circuit comprises: a voltage division circuit configured to receive the bias control signal and output a bias voltage signal based on a reference voltage signal; and a conversion circuit coupled with the voltage division circuit configured to receive the bias voltage signal and output the bias current signal.
5. 5 . The memory device of claim 4 , wherein the bias control signal comprises a first bias control sub-signal and a second bias control sub-signal, and wherein the voltage division circuit comprises: a first adjustable resistor comprising a first terminal, a second terminal, and a control terminal coupled with the first bias control sub-signal, wherein the first terminal is configured to receive the reference voltage signal; and a second adjustable resistor comprising a first terminal coupled with a second terminal of the first adjustable resistor, a second terminal, and a control terminal coupled with the second bias control sub-signal, wherein the second terminal of the first adjustable resistor is coupled with the voltage division circuit and output the bias voltage signal.
6. 6 . The memory device of claim 5 , wherein an adjustable range of the first adjustable resistor and an adjustable range of the second adjustable resistor are the same.
7. 7 . The memory device of claim 5 , wherein the first bias control sub-signal and the second bias control sub-signal are the same.
8. 8 . The memory device of claim 5 , wherein the control circuit is further configured to output a reference control signal according to a maximum data transfer rate supported by the memory device; and wherein the voltage division circuit further comprises a reference voltage generator coupled with the control circuit and configured to: receive the reference control signal from the control circuit, and output, based on the reference control signal, the reference voltage signal.
9. 9 . The memory device of claim 3 , wherein the configuration code comprises bits, and wherein the bits represent read latency (RL) information or write latency (WL) information corresponding to the data transfer rate.
10. 10 . The memory device of claim 9 , wherein the configuration code comprises 4 bits, wherein two of the 4 bits are configurable to generate 4 sets of bias control signals.
11. 11 . The memory device of claim 1 , further comprising: a clock frequency division circuit respectively coupled with the bias generation circuit and the clock buffer circuit and configured to, in response to receiving the target bias signal and a target clock signal from the clock buffer circuit, output a multi-path phase-splitting clock signal with adjusted frequency and phase; and a clock driving circuit coupled with the bias generation circuit and the clock frequency division circuit and configured to, in response to receiving the target bias signal and the multi-path phase-splitting clock signal, output the multi-path phase-splitting clock signal to a respective input/output circuit in the memory device.
12. 12 . The memory device of claim 1 , wherein the target bias signal and a power consumption required for the clock buffer circuit in response to caching the target bias signal increase with an increase in the data transfer rate.
13. 13 . A method of operating a memory device, comprising: receiving a bias control signal, wherein different bias control signals correspond to different data transfer rates of the memory device; generating a target bias signal based on the bias control signal; and adjusting, based on the target bias signal, a working current of a clock buffer circuit in the memory device.
14. 14 . The method of claim 13 , further comprising: receiving a configuration code to characterize the data transfer rate; and converting the configuration code to the bias control signal.
15. 15 . The method of claim 14 , wherein the target bias signal comprises a bias current signal, and wherein generating the target bias signal based on the bias control signal comprises: performing, in response to the bias control signal, voltage division processing on a reference voltage signal to generate a bias voltage signal; and converting the bias voltage signal to obtain the bias current signal.
16. 16 . The method of claim 14 , wherein the configuration code comprises bits; and the bits represent read latency (RL) information or write latency (WL) information corresponding to the data transfer rate.
17. 17 . The method of claim 16 , wherein the configuration code comprises 4 bits, and wherein two of the 4 bits are configurable to generate 4 sets of bias control signals.
18. 18 . The method of claim 15 , wherein the bias control signal comprises a first bias control sub-signal and a second bias control sub-signal, and wherein generating the target bias signal based on the bias control signal further comprises: receiving, by a first adjustable resistor, the reference voltage signal and the first bias control sub-signal; receiving, by a second adjustable resistor, the first bias control sub-signal; and outputting the bias control signal at a node to which the first adjustable resistor and the second adjustable resistor are coupled.
19. 19 . The method of claim 13 , further comprising: dividing a target clock signal into a multi-path phase-splitting clock signal with adjusted frequency and phase; and transferring, based on the target bias signal, the multi-path phase-splitting clock signal to a respective input/output circuit in the memory device.
20. 20 . A system, comprising: at least one memory device, comprising: a bias generation circuit configured to receive a bias control signal and output a target bias signal based on the bias control signal, wherein different bias control signals correspond to different data transfer rates of the memory device; and a clock buffer circuit coupled with the bias generation circuit and configured to receive the target bias signal and adjust a working current of the clock buffer circuit based on the target bias signal; and a memory controller coupled with the at least one memory device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is continuation of U.S. application Ser. No. 18/662,519, filed on May 13, 2024, entitled “A MEMORY SYSTEM AND OPERATION METHOD THEREOF,” which claims the benefit of and priority to Chinese Patent Application No. 202311545971X, which was filed Nov. 16, 2023, is titled “MEMORY DEVICE, OPERATION METHOD, AND MEMORY SYSTEM,” and is hereby incorporated herein by reference in its entirety. TECHNICAL FIELD The present application relates to the technical field of memories, and particularly to a memory device, an operation method, and a memory system. BACKGROUND With the development of technology, the data transfer rate of memory devices continues to increase. In other words, the memory devices can have operating modes with various data transfer rates. In order to enable the memory devices to support these data transfer rates, it is necessary to keep a clock input buffer (WCK IB) in a high-power-consumption operating state all the time. SUMMARY In view of this, examples of the present application provide a memory device and a memory system. In a first aspect, examples of the present application provide a memory device, comprising: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; anda clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device. In the above solution, the bias generation circuit includes a control sub-circuit and a generation sub-circuit, wherein the control sub-circuit is configured to obtain a configuration code to characterize the data transfer rate, perform conversion processing on the configuration code to generate a bias control signal, and transfer the bias control signal to the generation sub-circuit; andthe generation sub-circuit is coupled with the control sub-circuit, and configured to generate, in response to the bias control signal, the target bias signal. In the above solution, the control sub-circuit includes a storage circuit and a decoding circuit, wherein the storage circuit is configured to store the configuration code; andthe decoding circuit is connected with the storage circuit, and is configured to obtain the configuration code from the storage circuit, and perform conversion processing on the configuration code to generate the bias control signal. In the above solution, the target bias signal includes a bias current signal; and the generation sub-circuit includes a voltage division circuit and a conversion circuit, wherein the voltage division circuit is configured to perform, in response to the bias control signal, voltage division processing on a reference voltage signal to generate a bias voltage signal; andthe conversion circuit is configured to convert the bias voltage signal to obtain the bias current signal,wherein the reference voltage signal is obtained according to a maximum data transfer rate supported by the memory device. In the above solution, the bias control signal includes a first bias control sub-signal and a second bias control sub-signal. The voltage division circuit includes a first adjustable resistor and a second adjustable resistor, wherein a first end of the first adjustable resistor is connected to the reference voltage signal, a second end of the first adjustable resistor is connected with a first end of the second adjustable resistor, and a control end of the first adjustable resistor is connected to the first bias control sub-signal;a second end of the second adjustable resistor is grounded; and a control end of the second adjustable resistor is connected to the second bias control sub-signal,wherein under the control of the first bias control sub-signal and/or the second bias control sub-signal, the bias voltage signal is output at a joint of the first adjustable resistor and the second adjustable resistor. In the above solution, an adjustable range of the first adjustable resistor and that of the second adjustable resistor are the same. In the above solution, the first bias control sub-signal and the second bias control sub-signal are the same. In the above solution, the control sub-circuit is further configured to obtain a reference control signal according to a maximum data transfer rate supported by the memory device; and the voltage division circuit further includes a reference voltage generator, which is connected with the control sub-circuit, and is configured to obtain the reference control signal from the control sub-circuit, and output, in response to the reference control signal, the reference voltage signal. In the above solution, the configuration code includes a plurality of bits; and the plurality of bits represent read