US-20260128080-A1 - CLOCK CONTROL CIRCUIT, MEMORY, AND CLOCK CONTROL METHOD

Abstract

A clock control circuit includes: a delay adjustment circuit, receiving a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal, and a determination result signal, and adjusting delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal or adjust delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal according to the determination result signal in a duty cycle adjustment training mode; and a determination circuit, recording a phase sequence of the first phase clock signal and the third phase clock signal at self-refresh exit timing, then comparing the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing.

Inventors

• Zhiqiang Zhang

Assignees

• CXMT Corporation

Dates

Publication Date

20260507

Application Date

20260105

Priority Date

20240521

Claims (15)

1. 1 . A clock control circuit, applied to a memory, comprising: a delay adjustment circuit, configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal, and a determination result signal, adjust delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal or adjust delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal according to the determination result signal when the memory is in a duty cycle adjustment training mode, and output a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal; and a determination circuit, electrically connected with the delay adjustment circuit, and configured to record a phase sequence of the first phase clock signal and the third phase clock signal at self-refresh exit timing of the memory, then compare the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing with a phase sequence of the first phase clock signal and the third phase clock signal at previous self-refresh exit timing, and output the determination result signal according to whether the two phase sequences are consistent or not.
2. 2 . The clock control circuit according to claim 1 , wherein recording the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing of the memory comprises: receiving, by the memory, a no-operation NOP command at the self-refresh exit timing, and if the no-operation NOP command is sampled at a rising edge of the first phase clock signal, recording that the first phase clock signal leads the third phase clock signal in phase; and if the no-operation NOP command is sampled at a rising edge of the third phase clock signal, recording that the first phase clock signal lags the third phase clock signal in phase; and comparing the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing with the phase sequence of the first phase clock signal and the third phase clock signal at the previous self-refresh exit timing, and outputting the determination result signal according to whether the two phase sequences are consistent or not comprise: outputting the determination result signal with a logic value of 1 if the two phase sequences are consistent, and outputting the determination result signal with the logic value of 0 if the two phase sequences are inconsistent.
3. 3 . The clock control circuit according to claim 2 , wherein the delay adjustment circuit comprises: a control circuit, configured to receive a first set of control codes, a second set of control codes, and the determination result signal, output the first set of control codes as target control codes if the logic value of the determination result signal is 1, and output the second set of control codes as the target control codes if the logic value of the determination result signal is 0; wherein the first set of control codes is used for adjusting the delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal, and the second set of control codes is used for adjusting the delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal; and a delay circuit, electrically connected with the control circuit, and configured to receive the first phase clock signal, the second phase clock signal, the third phase clock signal, the fourth phase clock signal and the target control codes, adjust the delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal or adjust the delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal according to the target control codes, and output the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal.
4. 4 . The clock control circuit according to claim 3 , wherein the target control codes comprise a first target control code, a second target control code, a third target control code, and a fourth target control code, and the delay circuit comprises: a first delay sub-circuit, configured to receive the first phase clock signal and the first target control code, adjust the delay of the first phase clock signal according to the first target control code, and output the first target clock signal; a second delay sub-circuit, configured to receive the second phase clock signal and the second target control code, adjust the delay of the second phase clock signal according to the second target control code, and output the second target clock signal; a third delay sub-circuit, configured to receive the third phase clock signal and the third target control code, adjust the delay of the third phase clock signal according to the third target control code, and output the third target clock signal; and a fourth delay sub-circuit, configured to receive the fourth phase clock signal and the fourth target control code, adjust the delay of the fourth phase clock signal according to the fourth target control code, and output the fourth target clock signal.
5. 5 . The clock control circuit according to claim 4 , wherein the first set of control codes sequentially comprises a ground signal, a second phase control code, a third phase control code, and a fourth phase control code; the second set of control codes sequentially comprises the third phase control code, the fourth phase control code, the ground signal, and the second phase control code; and the control circuit comprises: a first selection unit, configured to receive the ground signal, the third phase control code, and the determination result signal, output the ground signal as the first target control code if the logic value of the determination result signal is 1, and output the third phase control code as the first target control code if the logic value of the determination result signal is 0; a second selection unit, configured to receive the second phase control code, the fourth phase control code, and the determination result signal, output the second phase control code as the second target control code if the logic value of the determination result signal is 1, and output the fourth phase control code as the second target control code if the logic value of the determination result signal is 0; a third selection unit, configured to receive the third phase control code, the ground signal, and the determination result signal, output the third phase control code as the third target control code if the logic value of the determination result signal is 1, and output the ground signal as the third target control code if the logic value of the determination result signal is 0; and a fourth selection unit, configured to receive the fourth phase control code, the second phase control code, and the determination result signal, output the fourth phase control code as the fourth target control code if the logic value of the determination result signal is 1, and output the second phase control code as the fourth target control code if the logic value of the determination result signal is 0.
6. 6 . The clock control circuit according to claim 5 , wherein the second phase control code, the third phase control code, and the fourth phase control code are stored and output by a mode register.
7. 7 . The clock control circuit according to claim 4 , wherein the first delay sub-circuit comprises a first capacitor unit and an even number of first inverters, wherein the even number of first inverters are sequentially connected, an input terminal of a first inverter at a head receives the first phase clock signal, an output terminal of a first inverter at a tail outputs the first target clock signal, and the first capacitor unit receives the first target control code and is connected to an output terminal of one of the first inverters; the second delay sub-circuit comprises a second capacitor unit and an even number of second inverters, wherein the even number of second inverters are sequentially connected, an input terminal of a second inverter at a head receives the second phase clock signal, an output terminal of a second inverter at a tail outputs the second target clock signal, and the second capacitor unit receives the second target control code and is connected to an output terminal of one of the second inverters; the third delay sub-circuit comprises a third capacitor unit and an even number of third inverters, wherein the even number of third inverters are sequentially connected, an input terminal of a third inverter at a head receives the third phase clock signal, an output terminal of a third inverter at a tail outputs the third target clock signal, and the third capacitor unit receives the third target control code and is connected to an output terminal of one of the third inverters; and the fourth delay sub-circuit comprises a fourth capacitor unit and an even number of fourth inverters, wherein the even number of fourth inverters are sequentially connected, an input terminal of a fourth inverter at a head receives the fourth phase clock signal, an output terminal of a fourth inverter at a tail outputs the fourth target clock signal, and the fourth capacitor unit receives the fourth target control code and is connected to an output terminal of one of the fourth inverters.
8. 8 . The clock control circuit according to claim 2 , wherein the determination circuit comprises: a latch, configured to receive a first mark signal and a second mark signal, wherein the first mark signal is used for indicating that the no-operation NOP command is sampled at the rising edge of the first phase clock signal at the self-refresh exit timing, the second mark signal is used for indicating that the no-operation NOP command is sampled at the rising edge of the third phase clock signal at the self-refresh exit timing, and output a phase flag signal at a first level if the first mark signal is in a valid state and output the phase flag signal at a second level if the second mark signal is in the valid state; and a comparison unit, electrically connected with the latch, and configured to receive and store the phase flag signal, compare a level state of the phase flag signal received at current self-refresh exit timing with a level state of the phase flag signal received at previous self-refresh exit timing, output the determination result signal with the logic value of 1 if the two level states are consistent, and output the determination result signal with the logic value of 0 if the two level states are inconsistent.
9. 9 . The clock control circuit according to claim 8 , wherein the latch is an SR latch, wherein a first terminal of the SR latch receives the first mark signal, a second terminal receives the second mark signal, and an output terminal outputs the phase flag signal.
10. 10 . A memory, comprising the clock control circuit according to claim 1 .
11. 11 . The memory according to claim 10 , further comprising: a receiving circuit, configured to receive an external clock signal and output an internal clock signal, the internal clock signal having a same frequency as the external clock signal; a frequency divider, electrically connected with the receiving circuit, and configured to receive the internal clock signal, divide the internal clock signal by two, and generate the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal; and a delay lock loop, electrically connected with the frequency divider and the clock control circuit, and configured to delay at least one of the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal such that at least one of the first phase clock signal, the second phase clock signal, the third phase clock signal, and the fourth phase clock signal has a phase difference with the external clock signal that is less than a preset value.
12. 12 . The memory according to claim 11 , wherein the memory conforms to DDR5 specification.
13. 13 . A clock control method, applied to a memory and comprising: recording a phase sequence of a first phase clock signal and a third phase clock signal at self-refresh exit timing of the memory, and comparing the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing with a phase sequence of the first phase clock signal and the third phase clock signal at previous self-refresh exit timing, so as to determine whether the two phase sequences are consistent or not; and adjusting, if the two phase sequences are consistent, delays of a second phase clock signal, the third phase clock signal, and a fourth phase clock signal when the memory is in a duty cycle adjustment training mode; and adjusting, if the two phase sequences are not consistent, delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode.
14. 14 . The clock control method according to claim 13 , wherein recording the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing of the memory comprises: receiving, by the memory, a no-operation NOP command at the self-refresh exit timing, and if the no-operation NOP command is sampled at a rising edge of the first phase clock signal, recording that the first phase clock signal leads the third phase clock signal in phase; and if the no-operation NOP command is sampled at a rising edge of the third phase clock signal, recording that the first phase clock signal lags the third phase clock signal in phase.
15. 15 . The clock control method according to claim 13 , wherein adjusting, if the two phase sequences are consistent, the delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode; and adjusting, if the two phase sequences are not consistent, the delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal when the memory is in the duty cycle adjustment training mode comprise: adjusting, if the two phase sequences are consistent, the delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal by using a first set of control codes when the memory is in the duty cycle adjustment training mode; and adjusting, if the two phase sequences are not consistent, the delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal by using a second set of control codes when the memory is in the duty cycle adjustment training mode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Patent Application No. PCT/CN2024/127587, filed on Oct. 28, 2024, which claims the benefit of Chinese Patent Application No. 202410651361.6, titled “CLOCK CONTROL CIRCUIT, MEMORY, AND CLOCK CONTROL METHOD”, filed with the China National Intellectual Property Administration (CNIPA) on May 21, 2024, the disclosures of which are incorporated herein by reference in their entireties. TECHNICAL FIELD Embodiments of the present disclosure relate to the technical field of semiconductors, and in particular, to a clock control circuit, a memory, and a clock control method. BACKGROUND A clock is a very important component of a digital circuit and provides a stable time reference such that various parts of the digital circuit can operate based on a predetermined time sequence. In memory, the clock also plays a very important role. Data in the memory is usually transmitted in a certain time sequence. A clock signal is capable of controlling the input and output of data, ensuring that data is read or written at the correct point in time. Through the synchronous action of the clock, the memory can coordinate with other digital circuit components, so as to ensure the accuracy and the reliability of data transmission. However, due to environmental influences, the external clock signal received by the memory may have a duty cycle variation, which may affect the normal operation of the internal clock of the memory. SUMMARY Embodiments of the present disclosure provide a clock control circuit, a memory, and a clock control method, which are at least beneficial for improving a phase difference between four-phase clock signals. In a first aspect, the embodiments of the present disclosure provide a clock control circuit, which is applied to a memory, and includes: a delay adjustment circuit, configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal, and a determination result signal, adjust delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal or adjust delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal according to the determination result signal when the memory is in a duty cycle adjustment training mode, and output a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal; anda determination circuit, electrically connected with the delay adjustment circuit, and configured to record a phase sequence of the first phase clock signal and the third phase clock signal at self-refresh exit timing of the memory, then compare the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing with a phase sequence of the first phase clock signal and the third phase clock signal at previous self-refresh exit timing, and output the determination result signal according to whether the two phase sequences are consistent or not. In some embodiments, recording the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing of the memory includes: receiving, by the memory, a no-operation NOP command at the self-refresh exit timing, and if the no-operation NOP command is sampled at a rising edge of the first phase clock signal, recording that the first phase clock signal leads the third phase clock signal in phase; and if the no-operation NOP command is sampled at a rising edge of the third phase clock signal, recording that the first phase clock signal lags the third phase clock signal in phase; and comparing the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing with the phase sequence of the first phase clock signal and the third phase clock signal at the previous self-refresh exit timing, and outputting the determination result signal according to whether the two phase sequences are consistent or not include: outputting the determination result signal with a logic value of 1 if the two phase sequences are consistent, and outputting the determination result signal with the logic value of 0 if the two phase sequences are inconsistent. In some embodiments, the delay adjustment circuit includes: a control circuit, configured to receive a first set of control codes, a second set of control codes, and the determination result signal, output the first set of control codes as target control codes if the logic value of the determination result signal is 1, and output the second set of control codes as the target control codes if the logic value of the determination result signal is 0; where the first set of control codes is used for adjusting the delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal, and the s