US-20260128081-A1 - MEMORY DEVICE

Abstract

A memory device includes a first memory cell array including a plurality of bit lines; a second memory cell array including a plurality of complementary bit lines corresponding to the plurality of bit lines, and arranged adjacent to the first memory cell array in a first direction; and a first bit line sense amplifier array having at least a portion overlapping the first memory cell array on the first memory cell array, and including a plurality of first bit line sense amplifiers connected to a plurality of first bit lines among the plurality of bit lines and a plurality of first complementary bit lines among the plurality of complementary bit lines.

Inventors

• Duckyoung Seo
• Kyu-Chang KANG

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250630

Priority Date

20241107

Claims (20)

1. 1 . A memory device comprising: a first memory cell array including a plurality of bit lines; a second memory cell array including a plurality of complementary bit lines corresponding to the plurality of bit lines, respectively, wherein the second memory cell array is arranged adjacent to the first memory cell array in a first lateral direction; and a first bit line sense amplifier array that at least partially overlaps the first memory cell array along a vertical direction, wherein the first bit line sense amplifier array comprises: a plurality of first bit line sense amplifiers connected to (i) a plurality of first bit lines of the plurality of bit lines and (ii) a plurality of first complementary bit lines of the plurality of complementary bit lines.
2. 2 . The memory device of claim 1 , wherein: the first memory cell array is on a first substrate, and the first bit line sense amplifier array is on a second substrate that is above the first substrate.
3. 3 . The memory device of claim 2 , wherein the second memory cell array is on the first substrate.
4. 4 . The memory device of claim 1 , further comprising: a second bit line sense amplifier array that at least partially overlaps the second memory cell array along the vertical direction, wherein the second bit line sense amplifier array comprises: a plurality of second bit line sense amplifiers connected to (i) a plurality of second bit lines, different from the plurality of first bit lines, of the plurality of bit lines, and (ii) a plurality of second complementary bit lines, different from the plurality of first complementary bit lines, of the plurality of complementary bit lines.
5. 5 . The memory device of claim 4 , wherein the second bit line sense amplifier array is on a same substrate as the first bit line sense amplifier array.
6. 6 . The memory device of claim 4 , wherein the plurality of first bit lines are connected to a plurality of first cell wirings, wherein the plurality of first cell wirings are connected to the plurality of first bit line sense amplifiers through a plurality of first bonding contacts that are in a first edge region of the first memory cell array, wherein the first edge region is non-adjacent to the second memory cell array, and wherein the plurality of second bit lines are connected to a plurality of second cell wirings, wherein the plurality of second cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of second bonding contacts that are in a second edge region of the first memory cell array, wherein the second edge region is adjacent to the second memory cell array.
7. 7 . The memory device of claim 6 , wherein the plurality of first complementary bit lines are connected to a plurality of third cell wirings, wherein the plurality of third cell wirings are connected to the plurality of first bit line sense amplifiers through a plurality of third bonding contacts that are in a third edge region of the second memory cell array, wherein the third edge region is adjacent to the first memory cell array, and wherein the plurality of second complementary bit lines are connected to a plurality of fourth cell wirings, wherein the plurality of fourth cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of fourth bonding contacts that are in a fourth edge region of the second memory cell array, wherein the second edge region is non-adjacent to the first memory cell array.
8. 8 . The memory device of claim 7 , wherein: the plurality of bit lines and the plurality of complementary bit lines extend in the first lateral direction, and the plurality of first cell wirings, the plurality of second cell wirings, the plurality of third cell wirings, and the plurality of fourth cell wirings extend in the first lateral direction.
9. 9 . The memory device of claim 8 , comprising a cell wiring layer on the first memory cell array and the second memory cell array, wherein the plurality of first cell wirings, the plurality of second cell wirings, the plurality of third cell wirings, and the plurality of fourth cell wirings are on the cell wiring layer.
10. 10 . The memory device of claim 4 , wherein: the plurality of first bit lines and the plurality of second bit lines are arranged alternately along a second lateral direction intersecting the first lateral direction, and the plurality of first complementary bit lines and the plurality of second complementary bit lines are arranged alternately along the second lateral direction.
11. 11 . The memory device of claim 4 , wherein: two first bit line sense amplifiers, of the plurality of first bit line sense amplifiers, are connected to two adjacent first bit lines of the plurality of first bit lines, wherein one second bit line of the plurality of second bit lines is disposed between the two adjacent first bit lines, and wherein the two first bit line sense amplifiers are spaced apart in the first lateral direction.
12. 12 . The memory device of claim 4 , wherein the plurality of first bit lines are connected to a plurality of first cell wirings, wherein the plurality of first cell wirings are connected to the plurality of first bit line sense amplifiers through a plurality of first bonding contacts that are in a first edge region of the first memory cell array, wherein the first edge region is non-adjacent to the second memory cell array, and wherein the plurality of second bit lines are connected to a plurality of second cell wirings, wherein the plurality of second cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of second bonding contacts that are in the first edge region.
13. 13 . The memory device of claim 12 , wherein the plurality of first complementary bit lines are connected to a plurality of third cell wirings, wherein the plurality of third cell wirings are connected to the plurality of first bit line sense amplifiers through a plurality of third bonding contacts that are in a second edge region of the second memory cell array, wherein the second edge region is non-adjacent to the first memory cell array, and wherein the plurality of second complementary bit lines are connected to a plurality of fourth cell wirings, wherein the plurality of fourth cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of fourth bonding contacts that are in the second edge region.
14. 14 . The memory device of claim 13 , wherein: two adjacent first bit lines, of the plurality of first bit lines, and two adjacent second bit lines, of the plurality of second bit lines, are arranged alternately along a second lateral direction intersecting the first lateral direction, and two adjacent first complementary bit lines, of the plurality of first complementary bit lines, and two adjacent second complementary bit lines, of the plurality of second complementary bit lines, are arranged alternately along the second lateral direction.
15. 15 . The memory device of claim 14 , wherein: two first bit line sense amplifiers, of the plurality of first bit line sense amplifiers, are connected to the two adjacent first bit lines, and wherein the two first bit line sense amplifiers are spaced apart in the first lateral direction.
16. 16 . A memory device comprising: a first substrate including: a first mat including a plurality of first memory cells and a plurality of bit lines connected to the plurality of first memory cells, and a second mat including a plurality of second memory cells and a plurality of complementary bit lines connected to the plurality of second memory cells; and a second substrate above the first substrate, wherein the second substrate comprises a bit line sense amplifier, wherein the bit line sense amplifier at least partially overlaps the first mat along a vertical direction, wherein the bit line sense amplifier is connected to (i) a first bit line of the plurality of bit lines and (ii) a first complementary bit line the plurality of complementary bit lines, and wherein the first complementary bit line corresponds to the first bit line.
17. 17 . The memory device of claim 16 , wherein: the plurality of bit lines are on the plurality of first memory cells, the plurality of complementary bit lines are on the plurality of second memory cells, and the first substrate includes a cell wiring layer comprising: a first cell wiring connecting the first bit line and the bit line sense amplifier, and a second cell wiring connecting of the first complementary bit line and the bit line sense amplifier.
18. 18 . The memory device of claim 17 , wherein: the first cell wiring overlaps the first mat along the vertical direction, and the second cell wiring overlaps the first mat and the second mat along the vertical direction.
19. 19 . The memory device of claim 17 , wherein the second substrate includes a plurality of through vias connecting the first cell wiring and the second cell wiring to the bit line sense amplifier.
20. 20 . A memory device comprising: a first memory cell array including a plurality of bit lines; a second memory cell array including a plurality of complementary bit lines, wherein the second memory cell array is adjacent to the first memory cell array in a first direction; a first bit line sense amplifier array on and at least partially overlapping with the first memory cell array along a vertical direction, wherein the first bit line sense amplifier array is connected to (i) a plurality of first bit lines of the plurality of bit lines and (ii) a plurality of first complementary bit lines of the plurality of complementary bit lines; and a second bit line sense amplifier array and at least partially overlapping with the second memory cell array along the vertical direction, wherein the second bit line sense amplifier array is connected to (i) a plurality of second bit lines, different from the plurality of first bit lines, of the plurality of bit lines, and (ii) a plurality of second complementary bit lines, different from the plurality of first complementary bit lines, of the plurality of complementary bit lines.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0157076 filed in the Korean Intellectual Property Office on Nov. 7, 2024, the entire contents of which are incorporated herein by reference. BACKGROUND Volatile memory devices, such as dynamic random access memories (DRAM), store a data by storing charges in a capacitive load (a capacitor) of a memory cell, and read a data by determining the charges stored in the capacitor. A bit line sense amplifier may be connected to the memory cell to sense the data stored in the memory cell. The bit line sense amplifier may detect and amplify the voltage difference between the bit line and a complementary bit line determined depending on the data stored in the memory cell. Meanwhile, when designing the DRAM by adopting an open bit line structure, a dummy bit line is required for sensing an outermost memory cell array block, which may be a factor that deteriorates the integration or fabrication efficiency of the semiconductor memory device, such as a gross die per wafer or a net die per wafer. SUMMARY Some aspects of this disclosure relate to memory devices that may provided higher gross die per wafer, and/or other advantages as discussed herein. A memory device according to some implementations of the present disclosure may include a first memory cell array including a plurality of bit lines; a second memory cell array including a plurality of complementary bit lines corresponding to the plurality of bit lines, and arranged adjacent to the first memory cell array in a first direction; and a first bit line sense amplifier array having at least a portion overlapping the first memory cell array on the first memory cell array, and including a plurality of first bit line sense amplifiers connected to a plurality of first bit lines among the plurality of bit lines and a plurality of first complementary bit lines among the plurality of complementary bit lines. A memory device according to some implementations of the present disclosure may include a first substrate including a first mat including a plurality of first memory cells and a plurality of bit lines connected to the plurality of first memory cells, and a second mat including a plurality of second memory cells and a plurality of complementary bit lines connected to the plurality of second memory cells; and a second substrate positioned above the first substrate and including a bit line sense amplifier connected to one the plurality of bit lines and one of the plurality of complementary bit lines corresponding to one of the plurality of bit lines and disposed on the first mat. A memory device according to some implementations of the present disclosure may include a first memory cell array including a plurality of bit lines; a second memory cell array including a plurality of complementary bit lines and arranged adjacent to the first memory cell array in a first direction; a first bit line sense amplifier array disposed on the first memory cell array and connected to a plurality of first bit lines among the plurality of bit lines and a plurality of first complementary bit lines among the plurality of complementary bit lines; and a second bit line sense amplifier array disposed on the second memory cell array and connected a plurality of second bit lines different from the plurality of first bit lines among the plurality of bit lines, and a plurality of second complementary bit lines different from the plurality of first complementary bit lines among the plurality of complementary bit lines. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating an example of a memory device. FIG. 2 is a perspective diagrammatic view illustrating an example of a memory device. FIG. 3 is a diagram illustrating an example of a memory device as shown in FIG. 2. FIG. 4 is a perspective diagrammatic view illustrating an example of a memory device. FIG. 5 is a diagram illustrating an example of a memory device as shown in FIG. 4. FIG. 6 is a diagram illustrating an example of a memory device. FIG. 7 is a diagram illustrating an example of a memory cell array included in a memory device. FIG. 8 is a circuit diagram illustrating an example of a bit line sense amplifier included in a memory device. FIG. 9 is a diagram illustrating an example of a memory device. FIG. 10 is a diagram illustrating an example of a memory device. FIG. 11 is a diagram illustrating an example of a memory device. FIG. 12 is a diagram illustrating an example of a. FIG. 13 is a perspective diagrammatic view illustrating an example of a memory device. FIG. 14 is a cross-sectional view of an example of a memory device. FIG. 15 is a cross-sectional view of am example of a memory device. FIG. 16 is a block diagram illustrating an example of a computing device. DETAILED DESCRIPTION In the following detailed description, certain examples are described by way of illustration. As thos