US-20260128082-A1 - Sense Amplifier Circuitry and Threshold Voltage Compensation

US20260128082A1US 20260128082 A1US20260128082 A1US 20260128082A1US-20260128082-A1

Abstract

Sense amplifiers for memory devices may include threshold voltage compensation circuitry configured to compensate a threshold voltage offset of a portion of the sense amplifier. Additionally, the sense amplifiers also perform pre-sensing of the portion of the sense amplifier. Moreover, the sense amplifier is configured to perform main sensing and latching in a phase after pre-sensing the portion of the sense amplifier.

Inventors

Wenlun Zhang
Hiroki Fujisawa
Shinichi Miyatake
Yuan He

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20251027

Claims (20)

1 . A method of operating a memory device, comprising: compensating a threshold voltage offset of a portion of a sense amplifier of the memory device, wherein the portion comprises a first pair of transistors each coupled to a respective digit line and a respective gut node of the sense amplifier and further comprises a second pair of transistors each cross-coupled to multiple gut nodes of the sense amplifier, wherein compensating the threshold voltage offset comprises alternating a supplied voltage to the second pair of transistors by alternating activation of a plurality of supply transistors; performing pre-sensing of the portion of the sense amplifier; and performing main sensing and latching in a phase after pre-sensing the portion of the sense amplifier.
2 . The method of claim 1 , wherein the plurality of supply transistors comprises: a first supply transistor configured to connect VSS to the second pair of transistors at a node during a first portion of the compensation of the threshold voltage offset; and a second supply transistor configured to connect a voltage higher than VSS to the node to bleed charge off more slowly than would occur with VSS.
3 . The method of claim 2 , wherein the second supply voltage is 100 to 300 mV above VSS.
4 . The method of claim 2 , wherein the higher voltage of the second supply voltage reduces power consumption during the compensation of the threshold voltage offset.
5 . The method of claim 1 , wherein compensating the threshold voltage offset of the portion of the sense amplifier comprises not performing threshold voltage compensation of a remaining portion of the sense amplifier when compensating the threshold voltage offset of the portion of the sense amplifier.
6 . The method of claim 5 , wherein the remaining portion comprises a P-type sense amplifier portion of the sense amplifier.
7 . The method of claim 6 , wherein the P-type sense amplifier portion of the sense amplifier comprises a plurality of P-type transistors that are cross-coupled with each other.
8 . The method of claim 7 , wherein the threshold voltage offset does not compensate for a threshold voltage offset of the plurality of P-type transistors.
9 . A sense amplifier, comprising: a first transistor coupled between a first node configured to receive an activation signal, a first digit line, and a second digit line, wherein the first digit line is configured to receive a first charge from one or more memory cells corresponding to the sense amplifier for sensing, the second digit line is configured to receive a second charge from the one or more memory cells and is complementary to the first digit line; a second transistor coupled between the first node, the first digit line, and a second digit line; a third transistor coupled between a first gut node corresponding to the first digit line, a second gut node corresponding to the second digit line, and a second node configured to receive a strobe signal; a fourth transistor coupled between the first gut node, the second gut node, and the second node; and threshold voltage compensation circuitry configured to: compensate for a threshold voltage offset between the third and fourth transistors during a voltage threshold compensation phase by supplying a first voltage to the second node during a first part of the voltage threshold compensation phase and by supplying a second voltage to the second node during a second part of the voltage compensation phase; pre-sense during a pre-sense phase; and sense and latch during a main sensing and latching phase after the pre-sense phase.
10 . The sense amplifier of claim 9 , wherein the threshold voltage compensation circuitry comprises: a first supply transistor configured to connect the first voltage to the second node during the first part of the voltage threshold compensation phase; and a second supply transistor configured to connect the second voltage to the second node during the second part of the voltage threshold compensation phase, wherein the second voltage is higher than the first voltage to bleed charge off of the more slowly than if bled using the first voltage.
11 . The sense amplifier of claim 9 , wherein the first voltage comprises VSS, and the second voltage comprises a voltage higher than VSS.
12 . The sense amplifier of claim 11 , wherein the second voltage is 100 to 300 mV above VSS.
13 . The sense amplifier of claim 11 , wherein the higher voltage of the second voltage relative to the first voltage reduces power consumption during the voltage threshold compensation phase.
14 . The sense amplifier of claim 9 , wherein: the first transistor comprises: a first terminal of the first transistor coupled to the first node; a second terminal of the first transistor coupled to the first digit line; and a third terminal of the first transistor coupled to the second digit line; and the second transistor comprises: a first terminal of the second transistor coupled to the first node; a second terminal of the second transistor coupled to the second digit line; and a third terminal of the second transistor coupled to the first digit line.
15 . The sense amplifier of claim 14 , wherein the second terminal of the first transistor comprises a gate terminal, and the second terminal of the second transistor comprises a gate terminal.
16 . A memory device, comprising: one or more memory cells configured to store data; a pair of digit lines coupled to the one or more memory cells; and a sense amplifier coupled to the pair of digit lines and comprising: a pair of cross-coupled transistors each coupled to a first node configured to receive a strobe signal and each of the pair of cross-coupled transistors coupled to a first gut node at a first terminal and a second gut node at a second terminal; the first gut node corresponding to a first digit line of the pair of digit lines; the second gut node corresponding to a second digit line of the pair of digit lines; a third transistor coupled to the first gut node and the second digit line; a fourth transistor coupled to the second gut node and the first digit line; and threshold voltage compensation circuitry configured to compensate for a threshold voltage offset during a voltage threshold compensation phase by selecting a supply voltage to the first node from a plurality of supply voltages.
17 . The memory device of claim 16 , wherein the threshold voltage compensation circuitry comprises: a first supply transistor configured to selectively supply a first voltage to the first node based on a first control signal; and a second supply transistor configured to selectively supply a second voltage to the first node based on a second control signal, wherein the plurality of supply voltages comprises the first voltage and the second voltage.
18 . The memory device of claim 17 , wherein the first voltage is VSS and the second voltage is higher than VSS to bleed charge off more slowly than VSS would during a second part of the voltage threshold compensation phase following a first part of the voltage threshold compensation phase where the first voltage is supplied to the first node.
19 . The memory device of claim 18 , wherein the threshold voltage compensation circuitry comprises a third supply transistor configured to selectively supply a third voltage to the first node based on a third control signal.
20 . The memory device of claim 19 , wherein the third voltage is lower than VSS and is configured to overdrive a strobe signal during a pre-sensing phase of the sense amplifier.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. Application No. 18/506,202, filed November 10, 2023, which claims priority to U.S. Application No. 63/487,448, filed February 28, 2023, each of which is incorporated by reference herein in its entirety for all purposes. BACKGROUND Field of the Present Disclosure Embodiments of the present disclosure relate generally to memory devices. More specifically, embodiments of the present disclosure relate to sense amplifiers of a memory device. DESCRIPTION OF REALTER ART Generally, a computing system may include electronic devices that, in operation, communicate information via electrical signals. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random-access memory (DRAM) device, a ferroelectric random-access memory (FeRAM) device, another random-access memory (RAM) device, and/or a hybrid device that incorporates more than one type of RAM. In this manner, the processor may communicate with the memory device, for example, to retrieve executable instructions, retrieve data to be processed, by the processor, and/or store data output from the processor. These memory devices utilize sense amplifiers used by the memory devices during read operations. Specifically, the sense circuitry of the memory device utilizes the sense amplifiers to receive low voltage signals and amplify the small voltages to enable the memory device to interpret the data properly. However, due to the large number of sense amplifiers in the memory device any excess consumption of resources (e.g., power) in a sense amplifier may impact the efficiency of the memory device’s resources even when the change in a single sense amplifier is relatively small. Furthermore, some sense amplifiers may be sensitive to threshold voltage mismatches between sense amplifier latch devices (e.g., NMOS and/or PMOS transistors) and may be used to compensate for these threshold voltage mismatches using threshold voltage compensation (VTC). However, VTC may use DC through-current that consumes a relatively large amount (e.g., 14%) of all power consumption of memory devices. The DC through-current may negatively impact VTC. Furthermore, pattern noise may significantly deteriorate a sense margin and hinder intrinsic VTC performance using traditional VTC techniques. Furthermore, corner-dependent noise may further complicate device enhancement/optimization. Embodiments of the present disclosure may be directed to one or more of the problems set forth above. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified block diagram illustrating certain features of a memory device having sense amplifiers, according to an embodiment of the present disclosure; FIG. 2 is a circuit diagram of an embodiment of the sense amplifiers of FIG. 1, according to an embodiment of the present disclosure; FIG. 3 is a circuit diagram of an alternative embodiment of the sense amplifiers of FIG. 1 that uses NMOS pre-sensing, according to an embodiment of the present disclosure; FIG. 4 is a graph of a timing diagram for using the sense amplifier of FIG. 3, according to an embodiment of the present disclosure; FIG. 5 is a flow diagram of an embodiment of operation using the sense amplifier of FIG. 3, according to an embodiment of the present disclosure; FIG. 6 is an alternative embodiment of the sense amplifier of FIG. 3 with overdriving to accelerate NMOS pre-sensing, according to an embodiment of the present disclosure; and FIG. 7 is a graph of a timing diagram for using the sense amplifier of FIG. 6, according to an embodiment of the present disclosure. DETAILED DESCRIPTION One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers’ specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. As previously discussed, the sense circuitry of the memory device utilizes the sense amplifiers to receive low voltage (e.g., low differential) signals and amplify the small voltage differences to enable the memory device to interpret the data properly. However, some embodiments of the sense amplifiers consume excess resources (e.g., power). Thus, as taught herein, the sense amplifiers may be modified to perform VTC for NMOS transistors (NSA VT) without performing VTC of PMOS transistors of the