US-20260128083-A1 - SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHODS OF THE SEMICONDUCTOR MEMORY DEVICE

US20260128083A1US 20260128083 A1US20260128083 A1US 20260128083A1US-20260128083-A1

Abstract

The present disclosure provides a capacitorless semiconductor memory device and a method of driving the capacitorless semiconductor memory device, the disclosed capacitorless semiconductor memory device may include a memory cell array comprising a plurality of memory cells including two transistors; a sensing amplifier and a clamping circuit connected to bit lines of the memory cell array; and a control section for controlling the sensing amplifier, the clamping circuit, and the memory cell array differently according to a first mode or a second mode.

Inventors

Cheol Seong Hwang

Assignees

SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Dates

Publication Date: 20260507
Application Date: 20251103
Priority Date: 20241105

Claims (13)

1 . A capacitorless semiconductor memory device, comprising: a memory cell array comprising a plurality of memory cells including two transistors; a sensing amplifier and a clamping circuit connected to bit lines of the memory cell array; and a control section for controlling the sensing amplifier, the clamping circuit, and the memory cell array differently according to a first mode or a second mode.
2 . The device of claim 1 , wherein the clamping circuit applies a clamping voltage value (V cl ), which is a value predetermined (δV th ) greater than a difference value between an operating voltage value (V dd ) of the bit line and a threshold voltage value (V th ) of the memory cell, to a memory cell of the bit line according to the first mode or the second mode.
3 . The device of claim 2 , wherein the control portion selects at least one of a plurality of read word lines included in the array of memory cells in the first mode, and reads data of a plurality of memory cells associated with the selected read word line.
4 . The device of claim 3 , wherein the control portion controls a sensing amplifier connected to a bit line of the memory cell array in the first mode to set a voltage of the bit line to an operating voltage value (V dd ), and to change a voltage of the selected read word line to 0 V, thereby reading data of a plurality of memory cells connected to the selected word line.
5 . The device of claim 4 , wherein in the first mode, the clamping circuitry causes a minimum value of the voltage on the bit line to be the clamping voltage value.
6 . The device of claim 2 , wherein the control portion selects at least one of the plurality of memory cells in the second mode, and reads data from the selected memory cell by controlling that an operating voltage value (V dd ) is applied to a bit line associated with the selected memory cell, and that a clamping voltage value (V cl ) of the clamping circuit is applied to a bit line of the unselected memory cell.
7 . The device of claim 6 , wherein in the second mode, the voltage of the selected word line is changed to 0 V, and an operating voltage value (V dd ) is applied to the unselected word line.
8 . The memory device of claim 7 , wherein the voltage drop of the unselected memory cell is not exceeded by the threshold voltage value by the clamping voltage value.
9 . A method of driving a memory cell array comprising a plurality of memory cells including two transistors, comprising: selecting a first mode or a second mode according to a selected memory cell in order to real data among memory cell arrays by a control unit, the memory cell arrays connected to a sensing amplifier and a clamping circuit through a bit line; and reading data from the memory cell using at least one of an operating voltage value (V dd ) provided by the sensing amplifier and a clamping voltage value (V cl ) provided by the clamping circuit, according to the selected first mode or second mode, wherein the clamping voltage value is set to a value predetermined (δV th ) greater than a difference value between the operating voltage value (V dd ) and a threshold voltage value (V th ) of the memory cell.
10 . The method of claim 9 , wherein the step of reading data from the memory cell reads data from a plurality of memory cells connected to the selected word line is performed by controlling a sensing amplifier connected to a bit line of the memory cell from which the data is to be read by setting a voltage of the bit line to an operating voltage value (V dd ), and changing a voltage of a word line of the memory cell from which the data is to be read to 0 V, when the first mode is selected.
11 . The method of claim 10 , wherein the clamping circuitry causes a minimum value of a voltage on the bit line in the first mode to be a value of the clamping voltage.
12 . The method of claim 9 , wherein the step of reading data from the memory cell selects at least one of the plurality of memory cells in the second mode, and reads data from the selected memory cell by controlling the sensing amplifier to apply an operating voltage value (V dd ) to bit lines associated with the selected memory cell, and controls the clamping circuit to apply a clamping voltage value (V cl ) to bit lines of the unselected memory cell.
13 . The method of claim 12 , wherein, in the second mode, a voltage of the selected word line is varied to 0 V, and an operating voltage value (V dd ) is applied to the unselected word line, such that a voltage drop of the unselected memory cell is not exceeded by the threshold voltage value by the clamping voltage value.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority of Korean Patent Application No. 10-2024-0155482, filed on Nov. 5, 2024, in the KIPO (Korean Intellectual Property Office), the disclosure of which is incorporated herein entirely by reference. BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory technology, and more particularly to a semiconductor memory device and an operating method of the semiconductor memory device. Description of the Related Art Today, a semiconductor memory that randomly writes and reads data at high speed is dynamic random access memory (DRAM), which is widely used in data storage devices or devices. DRAM includes a plurality of repeated memory cells, each of which typically includes a capacitor configured to store data information and a transistor configured to control the reading of data information from the capacitor structure. To facilitate the integrated development of such memory cells, a related art has developed techniques for using memory cells in a 2T0C structure. The 2T0C structure uses two transistors as memory elements and does not include a capacitor, which reduces the volume occupied by the memory cell. In addition, neighboring memory cells may be organized by sharing word lines and bit lines. However, these 2T0C DRAMs suffer from the problem that when a selected cell is read, it may be interfered with depending on the state of neighboring cells that share word lines and bit lines. For example, if the selected cell is off (data 0) and the three neighboring cells are all on (data 1), the selected cell has a higher probability of being interfered with by the three neighboring cells. Therefore, there is a great need to develop a 2TOC circuit that may solve this interference problem between neighboring memory cells. In particular, since DRAM may be used not only as a memory but also as a neuromorphic device for artificial intelligence, according to today's technology trends, it is necessary to develop a 2T0C circuit that may be used without interference from neighboring cells and without data reading errors. SUMMARY OF THE INVENTION The technical problem that the present invention aims to solve is to provide a semiconductor memory device that may read selected cells without interference from neighboring cells and may be used not only for memory but also for neuromorphic devices for artificial intelligence. Further, another technical problem that the present invention seeks to solve is to provide a method for driving a semiconductor memory device having the aforementioned advantages. A capacitorless semiconductor memory device according to one embodiment of the present invention includes a memory cell array comprising a plurality of memory cells comprising two transistors, a sensing amplifier and a clamping circuit connected to bit lines of the memory cell array; and a control section for controlling the sensing amplifier, the clamping circuit, and the memory cell array differently according to a first mode or a second mode. In this case, the clamping circuit applies a clamping voltage value (Vcl), which is a value that is a small fraction (δVth) greater than a difference between an operating voltage value (Vdd) of the bit line and a threshold voltage value (Vth) of the memory cell, to a bit line of the memory cell according to the first mode or the second mode. Further, the control unit selects at least one of a plurality of read word lines included in the memory cell array in the first mode, and reads data of a plurality of memory cells associated with the selected read word line. Further, in the first mode, the control part controls a sensing amplifier connected to a bit line of the memory cell array to set a voltage of the bit line to an operating voltage value (Vdd) and to change a voltage of the selected read word line to 0 V, thereby reading data of the plurality of memory cells connected to the selected word line. Further, the capacitorless semiconductor memory device according to one embodiment of the present invention, wherein in the first mode, the clamping circuitry causes the minimum value of the voltage on the bit line to be the clamping voltage value. The capacitorless semiconductor memory device according to the present invention, characterized in that in the second mode, the control portion selects at least one of the plurality of memory cells, and controls that an operating voltage value (Vdd) is applied to the bit lines associated with the selected memory cell, and that a clamping voltage value (Vcl) of the clamping circuit is applied to the bit lines of the unselected memory cell to read data from the selected memory cell. Further, the capacitorless semiconductor memory device according to one embodiment of the present invention is characterized in that in the second mode, the voltage of the selected word line is varied to 0 V, and an operating voltage value (Vdd) is applied to the