US-20260128085-A1 - SEMICONDUCTOR DEVICE INCLUDING PRE-CHARGE CIRCUIT AND A METHOD OF OPERATING THEREOF

US20260128085A1US 20260128085 A1US20260128085 A1US 20260128085A1US-20260128085-A1

Abstract

A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a memory cell connected to a bit line, and a biasing circuit configured to output a first bias voltage and a second bias voltage, the first bias voltage generated based on a threshold voltage of a p-type transistor, and the second bias voltage generated based on a threshold voltage of an n-type transistor. The semiconductor device includes a step-down circuit connected to the bit line and configured to receive the first and second bias voltages, the step-down circuit configured to output an output voltage to charge the bit line based on the first and second bias voltages.

Inventors

Motoki Tamura

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20260105

Claims (20)

1 . A semiconductor device, comprising: a step-down circuit connected between an input voltage and an output voltage, and configured to convert a power supply voltage to the output voltage to charge a bit line that is connected to a memory cell; wherein the step-down circuit comprises: a first p-type transistor having a gate terminal connected to a first bias voltage; a second p-type transistor having a gate terminal connected to the input voltage; a first n-type transistor having a gate terminal connected to a second bias voltage different from the first bias voltage; and a second n-type transistor having a gate terminal connected to the input voltage.
2 . The semiconductor device of claim 1 , wherein the first bias voltage is different from the second bias voltage.
3 . The semiconductor device of claim 1 , wherein the first bias voltage is equal to a third bias volage plus a first threshold voltage, and the second bias voltage is equal to the third bias volage minus a second threshold voltage.
4 . The semiconductor device of claim 1 , wherein the first p-type transistor having a first source/drain terminal and a second source/drain terminal, the second p-type transistor having a third source/drain terminal and a fourth source/drain terminal, the first n-type transistor having a fifth source/drain terminal and a sixth source/drain terminal, and the second n-type transistor having a seventh source/drain terminal and an eighth source/drain terminal.
5 . The semiconductor device of claim 4 , wherein the first source/drain terminal and the fifth source/drain terminal are connected to the input voltage.
6 . The semiconductor device of claim 5 , wherein the second source/drain terminal and the third source/drain terminal are connected to each other, and the sixth source/drain terminal and the seventh source/drain terminal are connected to each other, with the second source/drain terminal and the sixth source/drain terminal coupled to each other through a capacitor.
7 . The semiconductor device of claim 6 , wherein the fourth source/drain terminal and the eighth source/drain terminal are connected to the output voltage.
8 . The semiconductor device of claim 1 , further comprising: a biasing circuit comprising a first biasing portion configured to generate the first bias voltage, and a second biasing portion configured to generate the second bias voltage.
9 . The semiconductor device of claim 8 , wherein the first biasing portion includes a first operational amplifier with an output connected to a third transistor, the third transistor having a first threshold voltage configured to determine the first bias voltage.
10 . The semiconductor device of claim 9 , wherein the second biasing portion includes a second operational amplifier with an output connected to a fourth transistor, the fourth transistor having a second threshold voltage configured to determine the second bias voltage.
11 . A semiconductor device, comprising: a step-down circuit connected between an input voltage and an output voltage, and configured to convert a power supply voltage to the output voltage to charge a bit line that is connected to a memory cell; wherein the step-down circuit comprises: a first p-type transistor having a gate terminal connected to a first bias voltage; a second p-type transistor having a gate terminal connected to the input voltage; a first n-type transistor having a gate terminal connected to a second bias voltage different from the first bias voltage; and a second n-type transistor having a gate terminal connected to the input voltage; and wherein the first p-type transistor and the second p-type transistor are serially connected to each other between the input voltage and the output voltage, and the n-type transistor and the second n-type transistor are serially connected to each other between the input voltage and the output voltage.
12 . The semiconductor device of claim 11 , wherein the first p-type transistor having a first source/drain terminal and a second source/drain terminal, the second p-type transistor having a third source/drain terminal and a fourth source/drain terminal, the first n-type transistor having a fifth source/drain terminal and a sixth source/drain terminal, and the second n-type transistor having a seventh source/drain terminal and an eighth source/drain terminal.
13 . The semiconductor device of claim 12 , wherein the first source/drain terminal and the fifth source/drain terminal are connected to the input voltage.
14 . The semiconductor device of claim 13 , wherein the second source/drain terminal and the third source/drain terminal are connected to each other, and the sixth source/drain terminal and the seventh source/drain terminal are connected to each other, with the second source/drain terminal and the sixth source/drain terminal coupled to each other through a capacitor.
15 . The semiconductor device of claim 14 , wherein the fourth source/drain terminal and the eighth source/drain terminal are connected to the output voltage.
16 . The semiconductor device of claim 11 , further comprising: a biasing circuit comprising a first biasing portion configured to generate the first bias voltage, and a second biasing portion configured to generate the second bias voltage.
17 . The semiconductor device of claim 16 , wherein the first bias voltage is equal to a third bias volage plus a first threshold voltage of a third transistor of the first biasing portion, and the second bias voltage is equal to the third bias volage minus a second threshold voltage of a fourth transistor of the second biasing portion.
18 . A semiconductor device, comprising: a step-down circuit connected between an input voltage and an output voltage, and configured to convert a power supply voltage to the output voltage to charge a bit line that is connected to a memory cell; wherein the step-down circuit comprises: a first p-type transistor having a gate terminal connected to a first bias voltage; a second p-type transistor having a gate terminal connected to the input voltage; a first n-type transistor having a gate terminal connected to a second bias voltage different from the first bias voltage; and a second n-type transistor having a gate terminal connected to the input voltage; and wherein the first bias voltage is equal to a third bias volage plus a first threshold voltage of a third transistor, and the second bias voltage is equal to the third bias volage minus a second threshold voltage of a fourth transistor.
19 . The semiconductor device of claim 18 , wherein the first p-type transistor and the second p-type transistor are serially connected to each other between the input voltage and the output voltage, and the n-type transistor and the second n-type transistor are serially connected to each other between the input voltage and the output voltage.
20 . The semiconductor device of claim 18 , further comprising: a biasing circuit comprising a first biasing portion configured to generate the first bias voltage based on the first threshold voltage, and a second biasing portion configured to generate the second bias voltage based on the second threshold voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/169,588, filed Feb. 15, 2023, which claims the benefit of and priority to U.S. Provisional Patent App. No. 63/419,956, filed Oct. 27, 2022, the entire disclosure of each of which is incorporated herein by reference. BACKGROUND Developments in electronic devices, such as computers, portable devices, smart phones, internet of thing (IoT) devices, etc., have prompted increased demands for memory devices. In general, memory devices may be volatile memory devices and non-volatile memory devices. Volatile memory devices can store data while power is provided, but may lose the stored data once the power is shut off. Unlike volatile memory devices, non-volatile memory devices may retain data even after the power is shut off, but may be slower than the volatile memory devices. A charging circuit can pre-charge a bit line connected to the memory devices when writing to or reading from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a schematic block diagram of a memory device, in accordance with some embodiments. FIG. 2 illustrates a schematic of an example charging circuit, in accordance with some embodiments. FIG. 3 illustrates an example waveform of the input voltage that is provided to the step-down circuit of FIG. 2, in accordance with some embodiments. FIG. 4 illustrates a schematic of another example charging circuit, in accordance with some embodiments. FIG. 5 illustrates an example waveform of the input voltages that are provided to the charging circuit of FIG. 4, in accordance with some embodiments. FIGS. 6, 7, and 8 each illustrates a schematic of an example biasing circuit, in accordance with some embodiments. FIG. 9 illustrates a schematic of another example charging circuit, in accordance with some embodiments. FIG. 10 illustrates a schematic of another example charging circuit, in accordance with some embodiments. FIGS. 11, 12, 13, 14, 15, 16, and 17 each illustrates a schematic of an example biasing circuit, in accordance with some embodiments. FIG. 18 illustrates a flowchart of an example method of operating a semiconductor device, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over, or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” “top,” “bottom” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In typical DRAM memory systems, the bit line is pre-charged to be half of the supply voltage during a read operation of the DRAM memory cell connected to the bit line. Some pre-charge circuits include the usage of a low-dropout (LDO) regulator or a charge pump circuit. The power consumption of an LDO regulator can be high compared to the charge pump circuit. However, a drawback of charge pump circuits is higher voltage ripple or noise compared to the LDO regulator. Accordingly, a step-down circuit may be used to generate a voltage that is half of the input voltage. The step-down circuit can be used to reliably operate with a transistor that has a breakdown voltage lower than an input voltage. However, a drawback of the step-down circuit is t