US-20260128086-A1 - MEMORY AND OPERATION METHOD THEREOF, TRIM REGISTER, MEMORY SYSTEM

Abstract

Examples of the present disclosure disclose a memory and an operation method thereof, a trim register, a memory system, and an electronic device. The memory includes: a pre-charge circuit configured to: pre-charge a read node based on a pre-charge signal; a trim register coupled to the read node and configured to: output trim information latched in the trim register based on a read enable signal; and select whether to discharge the read node based on the trim information; and a read output circuit coupled to the read node and configured to: generate a read output signal based on a read output enable signal and a level of the read node, wherein the read output signal is to indicate whether the trim information is correct.

Inventors

• Simin Zhang
• Xiaodong MEI
• Huangpeng ZHANG
• Xiang Fu
• Chunyan Hu

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20250411

Priority Date

20241107

Claims (20)

1. 1 . A memory, comprising: a pre-charge circuit configured to: pre-charge a read node based on a pre-charge signal; a trim register coupled to the read node and configured to: output trim information latched in the trim register based on a read enable signal; and select whether to discharge the read node based on the trim information; and a read output circuit coupled to the read node and configured to: generate a read output signal based on a read output enable signal and a level of the read node, wherein the read output signal is to indicate whether the trim information is correct.
2. 2 . The memory of claim 1 , wherein the trim register comprises: a dynamic latch circuit configured to: latch the trim information; and an output circuit coupled to the dynamic latch circuit and configured to: output the trim information latched in the dynamic latch circuit based on the read enable signal; and discharge the read node in response to the trim information that is output being in a first state.
3. 3 . The memory of claim 2 , wherein, the pre-charge circuit is configured to: pre-charge the read node to a first level based on the pre-charge signal; the output circuit is configured to: discharge the read node from the first level to a second level based on the trim information that is output being in the first state; and the read output circuit is configured to: generate a first read output signal based on the read node being at the second level and the read output enable signal, wherein the first read output signal is to indicate whether the trim information in the first state is correct.
4. 4 . The memory of claim 2 , wherein the output circuit is further configured to: maintain a level of the read node in response to the trim information that is output being in a second state, wherein the second state is different from the first state.
5. 5 . The memory of claim 4 , wherein, the pre-charge circuit is configured to: pre-charge the read node to a first level based on the pre-charge signal; and the read output circuit is configured to: generate a second read output signal based on the read node being at the first level and the read output enable signal, wherein the second read output signal is to indicate whether the trim information in the second state is correct.
6. 6 . The memory of claim 2 , wherein: the output circuit comprises a first transistor and a second transistor; a first terminal of the first transistor is coupled to a first power terminal, a second terminal of the first transistor is coupled to a first terminal of the second transistor, and a control terminal of the first transistor is configured to receive the read enable signal; and a second terminal of the second transistor is coupled to the read node, and a control terminal of the second transistor is configured to receive the trim information.
7. 7 . The memory of claim 6 , wherein: the trim register further comprises an address selection circuit comprising at least one third transistor; a first terminal of the third transistor is coupled to the dynamic latch circuit, a second terminal of the third transistor is coupled to the first power terminal, and a control terminal of the third transistor is configured to receive an address signal; and the first terminal of the first transistor is coupled to the first power terminal through the third transistor.
8. 8 . The memory of claim 1 , wherein the trim register comprises a plurality of trim registers commonly coupled to the read node, and the memory further comprises: a latch circuit, wherein an input terminal of the latch circuit is coupled to the read output circuit, an output terminal of the latch circuit is coupled to a pin, and the latch circuit is configured to: latch read output data in the read output signal, wherein the read output data is to indicate whether the trim information latched in the corresponding trim register is correct.
9. 9 . The memory of claim 1 , further comprising: a control logic circuit coupled to the pre-charge circuit, the trim register, and the read output circuit respectively and configured to: generate the pre-charge signal at a first time instant; and generate the read enable signal at a second time instant after the first time instant.
10. 10 . The memory of claim 1 , wherein the pre-charge circuit comprises a fourth transistor, and wherein a first terminal of the fourth transistor is coupled to the read node, a second terminal of the fourth transistor is coupled to a second power terminal, and a control terminal of the fourth transistor is configured to receive the pre-charge signal.
11. 11 . An operation method of a memory, comprising: pre-charging a read node based on a pre-charge signal; outputting trim information latched in a trim register based on a read enable signal; discharging the read node in response to the trim information that is output being in a first state, wherein the trim register is coupled to the read node; and generating a first read output signal based on the read node being discharged to a second level and a read output enable signal, wherein the first read output signal is to indicate whether the trim information in the first state is correct.
12. 12 . The operation method of claim 11 , wherein, pre-charging a read node based on a pre-charge signal comprises: pre-charging the read node to a first level based on the pre-charge signal, wherein the first level is greater than the second level; and discharging the read node in response to the trim information that is output being in a first state comprises: discharging the read node from the first level to the second level in response to the trim information that is output being in the first state.
13. 13 . The operation method of claim 11 , further comprising: maintaining the read node at a first level in response to the trim information that is output being in a second state, wherein the second state is different from the first state, and the first level is greater than the second level.
14. 14 . The operation method of claim 13 , further comprising: generating a second read output signal based on the read node being at the first level and the read output enable signal, wherein the second read output signal is to indicate whether the trim information in the second state is correct.
15. 15 . The operation method of claim 14 , wherein pre-charging a read node based on a pre-charge signal comprises: pre-charging the read node to the first level based on the pre-charge signal.
16. 16 . The operation method of claim 14 , wherein the trim register comprises a plurality of trim registers commonly coupled to the read node, and the operation method further comprises: latching read output data in the first read output signal or the second read output signal, wherein the read output data is to indicate whether the trim information latched in the corresponding trim register is correct, respectively.
17. 17 . A trim register, comprising: a dynamic latch circuit configured to: latch trim information; and an output circuit coupled to the dynamic latch circuit and configured to: output the trim information latched in the dynamic latch circuit based on a read enable signal; and discharge a read node from a first level to a second level in response to the trim information that is output being in a first state.
18. 18 . The trim register of claim 17 , wherein the output circuit is further configured to: maintain the read node at the first level in response to the trim information that is output being in a second state.
19. 19 . The trim register of claim 17 , wherein: the output circuit comprises a first transistor and a second transistor; a first terminal of the first transistor is coupled to a first power terminal, a second terminal of the first transistor is coupled to a first terminal of the second transistor, and a control terminal of the first transistor is configured to receive the read enable signal; and a second terminal of the second transistor is coupled to the read node, and a control terminal of the second transistor is configured to receive the trim information.
20. 20 . The trim register of claim 19 , further comprising: an address selection circuit comprising at least one third transistor, wherein a first terminal of the third transistor is coupled to the dynamic latch circuit, and a second terminal of the third transistor is coupled to the first power terminal, a control terminal of the third transistor is configured to receive an address signal, and the first terminal of the first transistor is coupled to the first power terminal through the third transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority to Chinese Patent Application No. 202411587929.9, which was filed Nov. 7, 2024, and is hereby incorporated herein by reference in its entirety. TECHNICAL FIELD Examples of the present disclosure relate to the field of memory technology, including, but not limited to, a memory and an operation method thereof, a trim register, a memory system, and an electronic device. BACKGROUND A memory is categorized as a volatile memory or a non-volatile memory based on whether stored data is retained in the event of a power failure, wherein a volatile memory with data loss in the event of a power failure may include a static random access memory (SRAM) and dynamic random access memory (DRAM). After the memory has been manufactured, the impact of process deviations, layout errors, and the like on the memory may be adjusted through trimming test, thereby improving memory performance. For example, the memory may adjust its operation parameters by accessing trim information stored in a trim register. SUMMARY According to a first aspect of the examples of the present disclosure, a memory is provided, comprising: a pre-charge circuit configured to: pre-charge a read node based on a pre-charge signal; a trim register coupled to the read node and configured to: output trim information latched in the trim register based on a read enable signal; and select whether to discharge the read node based on the trim information; and a read output circuit coupled to the read node and configured to: generate a read output signal based on a read output enable signal and a level of the read node, wherein the read output signal is to indicate whether the trim information is correct. In some examples, the trim register comprises: a dynamic latch circuit configured to: latch the trim information; and an output circuit coupled to the dynamic latch circuit and configured to: output the trim information latched in the dynamic latch circuit based on the read enable signal; and discharge the read node in response to the trim information that is output being in a first state. In some examples, the pre-charge circuit is configured to: pre-charge the read node to a first level based on the pre-charge signal; the output circuit is configured to: discharge the read node from the first level to a second level based on the trim information that is output being in the first state; and the read output circuit is configured to: generate a first read output signal based on the read node being at the second level and the read output enable signal, wherein the first read output signal is to indicate whether the trim information in the first state is correct. In some examples, the output circuit is further configured to: maintain a level of the read node in response to the trim information that is output being in a second state, wherein the second state is different from the first state. In some examples, the pre-charge circuit is configured to: pre-charge the read node to a first level based on the pre-charge signal; and the read output circuit is configured to: generate a second read output signal based on the read node being at the first level and the read output enable signal, wherein the second read output signal is to indicate whether the trim information in the second state is correct. In some examples, the output circuit comprises a first transistor and a second transistor, and wherein, a first terminal of the first transistor is coupled to a first power terminal, a second terminal of the first transistor is coupled to a first terminal of the second transistor, and a control terminal of the first transistor is configured to receive the read enable signal; and a second terminal of the second transistor is coupled to the read node, and a control terminal of the second transistor is configured to receive the trim information. In some examples, the trim register further comprises an address selection circuit comprising at least one third transistor, and wherein, a first terminal of the third transistor is coupled to the dynamic latch circuit, a second terminal of the third transistor is coupled to the first power terminal, and a control terminal of the third transistor is configured to receive an address signal; and the first terminal of the first transistor is coupled to the first power terminal through the third transistor. In some examples, the trim register comprises a plurality of trim registers commonly coupled to the read node, and the memory further comprises: a latch circuit, wherein an input terminal of the latch circuit is coupled to the read output circuit, an output terminal of the latch circuit is coupled to a pin, and the latch circuit is configured to: latch read output data in the read output signal, wherein the read output data is to indicate whether the trim information latched in the corresponding trim register is correct. In some examples, the memory further co