US-20260128087-A1 - GATE-ALL-AROUND MEMORY DEVICES

US20260128087A1US 20260128087 A1US20260128087 A1US 20260128087A1US-20260128087-A1

Abstract

Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

Inventors

Jhon Jhy Liaw

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251229

Claims (20)

1 . A Static Random Access Memory (SRAM) cell, comprising: a first fin-shaped vertical stack over a first p-type well; a second fin-shaped vertical stack over an n-type well adjacent the first p-type well; a third fin-shaped vertical stack over the n-type well; a fourth fin-shaped vertical stack over a second p-type well adjacent the n-type well; a first dielectric fin between the first fin-shaped vertical stack and the second fin-shaped vertical stack; a second dielectric fin between the second fin-shaped vertical stack and the third fin-shaped vertical stack; and a third dielectric fin between the third fin-shaped vertical stack and the fourth fin-shaped vertical stack.
2 . The SRAM cell of claim 1 , wherein the first fin-shaped vertical stack includes a first pass-gate transistor and a first pull-down transistor, wherein the second fin-shaped vertical stack includes a first pull-up transistor, wherein the third fin-shaped vertical stack includes a second pull-up transistor, wherein the fourth fin-shaped vertical stack includes a second pass-gate transistor and a second pull-down transistor.
3 . The SRAM cell of claim 1 , further comprising: a fourth dielectric fin adjacent to the first fin-shaped vertical stack; and a fifth dielectric fin adjacent to the fourth fin-shaped vertical stack.
4 . The SRAM cell of claim 3 , wherein the fourth dielectric fin and the fifth dielectric fin define two ends of the SRAM cell.
5 . The SRAM cell of claim 3 , further comprising: a first gate cut dielectric feature disposed on the fourth dielectric fin; and a second gate cut dielectric feature disposed on the fifth dielectric fin.
6 . The SRAM cell of claim 1 , further comprising: an isolation feature among the first fin-shaped vertical stack, the second fin-shaped vertical stack, the third fin-shaped vertical stack, and the fourth fin-shaped vertical stack, wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin is disposed over the isolation feature.
7 . The SRAM cell of claim 1 , wherein each of the first fin-shaped vertical stack and the fourth fin-shaped vertical stack comprises a first width (W 1 ), wherein each of second fin-shaped vertical stack and the third fin-shaped vertical stack comprises a second width (W 2 ), and wherein a ratio (W 1 /W 2 ) of the first width W 1 to the second width W 2 is between about 1.1 and about 3.0.
8 . The SRAM cell of claim 1 , where each of the first dielectric fin, the second dielectric fin, and the third dielectric fin comprises one or more dielectric materials selected from a group consisting of silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, silicon nitride, aluminum oxide, yittrium oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide.
9 . The SRAM cell of claim 1 , wherein the first dielectric fin is disposed directly over an interface between the first p-type well and the n-type well.
10 . The SRAM cell of claim 1 , wherein the third dielectric fin is disposed directly over an interface between the n-type well and the second p-type well.
11 . A Static Random Access Memory (SRAM) cell, comprising: a first fin-shaped vertical stack disposed over a first fin over a first p-type well; a second fin-shaped vertical stack disposed over a second fin over an n-type well adjacent the first p-type well; a third fin-shaped vertical stack over the n-type well; a fourth fin-shaped vertical stack over a second p-type well adjacent the n-type well; a first source/drain feature disposed over the first fin and comprising n-type dopants; a second source/drain feature disposed over the second fin and comprising p-type dopants; a first dielectric fin between the first fin-shaped vertical stack and the second fin-shaped vertical stack and between the first source/drain feature and the second source/drain feature, the first dielectric fin extending to a first level of an upper surface of the second source/drain feature adjacent the second source/drain feature and to the first level adjacent the first fin-shaped vertical stack and the second fin-shaped vertical stack; a second dielectric fin between the second fin-shaped vertical stack and the third fin-shaped vertical stack and adjacent the second source/drain feature, the second dielectric fin extending to at least the first level adjacent the second source/drain feature and being recessed to a second level different than the first level adjacent the first fin-shaped vertical stack and the second fin-shaped vertical stack; a third dielectric fin between the third fin-shaped vertical stack and the fourth fin-shaped vertical stack; and a source/drain contact spanning over the first dielectric fin to interface the first source/drain feature and the second source/drain feature.
12 . The SRAM cell of claim 11 , wherein the first fin-shaped vertical stack includes a first pass-gate transistor and a first pull-down transistor, wherein the second fin-shaped vertical stack includes a first pull-up transistor, wherein the third fin-shaped vertical stack includes a second pull-up transistor, wherein the fourth fin-shaped vertical stack includes a second pass-gate transistor and a second pull-down transistor.
13 . The SRAM cell of claim 11 , further comprising: a fourth dielectric fin adjacent to the first fin-shaped vertical stack; and a fifth dielectric fin adjacent to the fourth fin-shaped vertical stack, wherein each of the fourth dielectric fin and the fifth dielectric fin comprises: a first layer, and a second layer wrapped around by the first layer, wherein a composition of the first layer is different from a composition of the second layer.
14 . The SRAM cell of claim 13 , wherein the fourth dielectric fin and the fifth dielectric fin define two ends of the SRAM cell.
15 . The SRAM cell of claim 13 , further comprising: a first gate cut dielectric feature disposed on the fourth dielectric fin; and a second gate cut dielectric feature disposed on the fifth dielectric fin.
16 . The SRAM cell of claim 11 , further comprising: an isolation feature among the first fin-shaped vertical stack, the second fin-shaped vertical stack, the third fin-shaped vertical stack, and the fourth fin-shaped vertical stack, wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin is disposed over the isolation feature.
17 . A memory cell, comprising: a first vertical stack of nanostructures over a first p-type well; a second vertical stack of nanostructures over an n-type well adjacent the first p-type well; a third vertical stack of nanostructures over the n-type well; a fourth vertical stack of nanostructures over a second p-type well adjacent the n-type well; a first dielectric fin between the first vertical stack of nanostructures and the second vertical stack of nanostructures; a second dielectric fin between the second vertical stack of nanostructures and the third vertical stack of nanostructures; and a third dielectric fin between the third vertical stack of nanostructures and the fourth vertical stack of nanostructures.
18 . The memory cell of claim 17 , further comprising: a gate structure disposed over the first vertical stack of nanostructures and the second vertical stack of nanostructures, wherein the gate structure wraps around each of the first vertical stack of nanostructures and each of the second vertical stack of nanostructures.
19 . The memory cell of claim 17 , wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin comprises: a first layer; and a second layer disposed in the first layer, wherein a composition of the first layer is different from a composition of the second layer.
20 . The memory cell of claim 19 , wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin further comprises a cap layer disposed on the first layer and the second layer.

Description

PRIORITY DATA This application is a divisional application of U.S. patent application Ser. No. 18/341,209, titled “GATE-ALL-AROUND MEMORY DEVICES” and filed Jun. 26, 2023, which is a divisional application of U.S. patent application Ser. No. 17/397,137, titled “GATE-ALL-AROUND MEMORY DEVICES” and filed Aug. 9, 2021, now U.S. Pat. No. 11,688,456, issued Jun. 27, 2023, which is a divisional application of U.S. patent application Ser. No. 16/547,858, titled “GATE-ALL-AROUND MEMORY DEVICES” and filed Aug. 22, 2019, now U.S. Pat. No. 11,087,831, issued Aug. 10, 2021. U.S. patent application Ser. No. 18/341,209, U.S. Application No. Ser. No. 17/397,137, and U.S. application Ser. No. 16/547,858 are herein incorporated by references in their entireties. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. For example, as integrated circuit (IC) technologies progress towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors (both also referred to as non-planar transistors) are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. A FinFET has an elevated channel wrapped by a gate on more than one side (for example, the gate wraps a top and sidewalls of a “fin” of semiconductor material extending from a substrate). Compared to planar transistors, such configuration provides better control of the channel and drastically reduces SCEs (in particular, by reducing sub-threshold leakage (i.e., coupling between a source and a drain of the FinFET in the “off” state)). A GAA transistor has a gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. The channel region of the GAA transistor may be formed from nanowires, nanosheets, other nanostructures, and/or other suitable structures. In some implementations, such channel region includes multiple nanostructures (which extend horizontally, thereby providing horizontally-oriented channels) vertically stacked. Such GAA transistor can be referred to as a vertically-stacked horizontal GAA (VGAA) transistor. A static random access memory (SRAM) cell has become a popular storage unit of high speed communication, high-density storage, image processing and system-on-chip (SOC) products. Although existing SRAM cells have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the drawings appended illustrate only typical embodiments of this invention and are therefore not to be considered limiting in scope, for the invention may apply equally well to other embodiments. FIG. 1 illustrates a circuit diagram of an SRAM cell. FIG. 2 illustrates a layout of an SRAM cell in accordance with some embodiments of the present disclosure. FIG. 3 illustrates a cross-sectional view of the layout in FIG. 2 along line A-A′, according to various aspects of the present disclosure. FIG. 4 illustrates a cross-sectional view of the layout in FIG. 2 along line B-B′, according to various aspects of the present disclosure. FIG. 5 illustrates a cross-sectional view of the layout in FIG. 2 along line C-C′, according to various aspects of the present disclosure. FIG. 6 illustrates a cross-sectional view of the layout in FIG. 2 along line D-D′, according to various aspects of the present disclosure. FIGS. 7A, 7B and 7C illustrate schematic cross-sectional views of a dielectric fin, according to various aspects of the present disclosure.