US-20260128088-A1 - BURST ACCESS MEMORY AND METHOD OF OPERATING A BURST ACCESS MEMORY

US20260128088A1US 20260128088 A1US20260128088 A1US 20260128088A1US-20260128088-A1

Abstract

A burst access memory comprises a memory array comprising a plurality of memory macros comprising an array of memory cells in rows and columns. The memory cells in each column are connected by at least one local bit line. The array of memory cells and local bit lines define the memory macro. A plurality of global bit lines are each connectable to several corresponding local bit lines. A controller schedules a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros. The plurality of macro accesses are scheduled to start with a predefined delay in relation to each other. Each macro access is divided into a plurality of ordered sub-operations. Consecutive macro accesses are directed to different memory macros and different columns. Data for consecutive macro accesses are arranged in the different memory macros and columns to match the consecutive macro accesses.

Inventors

Babak Mohammadi

Assignees

XENERGIC AB

Dates

Publication Date: 20260507
Application Date: 20250929
Priority Date: 20210505

Claims (20)

1 . A burst access memory comprising: a memory array comprising a plurality of memory macros, each memory macro comprising an array of memory cells without read/write logic arranged in rows and columns; a controller configured to schedule a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros, wherein the plurality of macro accesses are scheduled to start with a predefined delay in relation to each other, wherein each macro access is divided into a plurality of ordered sub-operations, and wherein consecutive macro accesses are directed to different memory macros and different columns, wherein data for consecutive macro accesses are arranged in the different memory macros and the different columns to match the consecutive macro accesses.
2 . The burst access memory according to claim 1 , further comprising an input and/or output multiplexer, wherein the input and/or output multiplexer is shared between the memory macros.
3 . The burst access memory according to claim 1 , wherein the plurality of global bit lines are connected to the input and/or output multiplexer, or wherein the plurality of global bit lines are connected to read or write circuitry, such as sense amplifiers, that are connected to the input and/or output multiplexer.
4 . The burst access memory according to claim 1 , wherein a new macro access is scheduled to start on every clock cycle, every second clock cycle, or every fourth clock cycle, of a clock signal.
5 . The burst access memory according to claim 1 , wherein the macro accesses to the memory macros are multi-cycle macro accesses.
6 . The burst access memory according to claim 1 , wherein the burst access memory is configured to operate without a registered output read buffer.
7 . The burst access memory according to claim 1 , wherein the plurality of macro accesses are composed of alternating read and write accesses or composed of a number of read accesses followed by a number of write accesses.
8 . The burst access memory according to claim 1 , wherein at least one of the global bit lines is connectable to multiple local bit lines in the same macro.
9 . The burst access memory according to claim 1 , wherein data read from consecutive macro accesses are time-multiplexed.
10 . The burst access memory according to claim 1 , further comprising an input and/or output multiplexer synchronized with the plurality of macro accesses such that data read from the consecutive macro accesses are routed to an output, wherein output data of the consecutive macro accesses are delivered to output ports on every clock cycle of the clock signal, or such that input data delivered ports on every clock cycle of the clock signal from input ports are written to the memory cells in the consecutive macro accesses.
11 . The burst access memory according to claim 1 , further comprising at least two parallel input and/or output multiplexers, wherein data read from the consecutive macro accesses are alternatingly routed to/from the two parallel input and/or output multiplexers.
12 . The burst access memory according to claim 1 , wherein data read from the consecutive macro accesses are alternatingly routed to one output multiplexer and/or wherein write data for consecutive macro accesses is alternatingly routed from an input port, or wherein data read from the consecutive macro accesses are alternatingly routed to a plurality of output ports and/or wherein write data is alternatingly routed from a plurality of input ports.
13 . The burst access memory according to claim 1 , configured to operate with different internal voltage domains, wherein the memory array is supplied with a voltage lower than the rest of the logic of the burst access memory, or wherein the memory array is supplied with a voltage greater than the rest of the logic of the burst access memory.
14 . The burst access memory according to claim 1 , wherein the plurality of memory macros, row selection logic and column logic operate at different voltage levels depending on whether a write operation or a read operation is performed.
15 . The burst access memory according to claim 1 , further comprising a separate initial burst memory buffer, wherein the controller is configured to read data from the separate initial burst memory buffer at every clock cycle during a latency period corresponding to the time it takes for the memory array to deliver read data, or wherein the controller is configured to write data to the separate initial burst memory buffer at every clock cycle during a latency period corresponding to the time it takes to write first data to the memory array.
16 . The burst access memory according to claim 1 , wherein the memory macros have different sizes.
17 . The burst access memory according to claim 1 , wherein the controller is configured to generate the plurality of macro accesses to the memory macros in an order based on timing and/or response time of individual memory macro accesses and/or macro access size.
18 . The burst access memory according to claim 1 , wherein a predefined macro access is skipped at least every second time and/or wherein a number of predefined macro accesses are accessed alternatingly in a sequence of macro accesses.
19 . The burst access memory according to claim 1 , wherein a timing unit is configured to arrange accesses in an order such that macro accesses taking longer than a predefined access time are skipped at least every second time.
20 . A method of operating a burst access memory comprising a plurality of memory macros, each memory macro comprising an array of memory cells without read/write logic arranged in rows and columns, the method comprising the steps of: generating a plurality of macro accesses to the memory macros, wherein the plurality of macro accesses are scheduled to start with a predefined delay in relation to each other, wherein each macro access is divided into a plurality of ordered sub-operations, and wherein consecutive macro accesses are directed to different memory macros and different columns, wherein data for consecutive memory accesses are arranged in the different memory macros and the different columns to match the consecutive macro accesses.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation application of U.S. Ser. No. 18/558,695 filed Nov. 2, 2023, which is the U.S. National Stage of PCT/EP 2022/062099 filed on May 5, 022, which claims priority to European Patent Application 21172323.4 filed on May 5, 2021, the entire content of both are incorporated herein by reference in their entirety. FIELD OF THE INVENTION The present disclosure relates to a burst access memory having internal mechanisms and structures for improving access speed and/or power consumption. BACKGROUND OF THE INVENTION Memories, for example Static Random Access Memories (SRAM), are widely used in integrated circuits and may account for a significant portion of the critical timing path in a digital design, for example, in a digital ASIC (Application Specific Integrated Circuit). A typical memory cell of an SRAM memory is a six-transistor (6T) memory cell made up of six MOSFETs. Each bit is stored on four transistors that form two cross-coupled inverters. In addition to the four transistors, the two cross-coupled inverters are connected to a bit line and an inverted bit line through two further access transistors, which are controlled by a common word line in the standard single-port 6T SRAM cell. Other types of SRAM cells exist. Memory cells in SRAMs are typically being accessed using an address which is decoded to feed or access the proper word line and bit lines. The time it takes to access a memory is often a limiting factor in circuit design, which are required to be clocked at increasingly higher frequencies. If the time that it takes for the memory to output a data is greater than the clock period at which the circuit operates, the designer can reduce the clock frequency of the design, which may have a performance impact, or apply other techniques, such as splitting the memory into several smaller instances. One technique to speed up accessing of memories is to use burst accesses. For burst accesses the memory will start reading or writing at a given address and then continue reading or writing data from/to consecutive addresses. This can save some decoding time. However, employing burst accesses may not be enough to meet the design targets with respect to speed (clock frequency) and operating voltage for a given process technology. It would thus be beneficial to have a burst access memory capable of operating at higher clock frequencies relative to the operating voltage for a given process technology. SUMMARY OF THE INVENTION The present disclosure relates to a burst access memory with improved relative read and write speeds. When accessing a memory, external commands in the form of enable signals, addresses and data need to be decoded and propagated to the memory array, at which an access needs to be performed. When data is read, the data needs to pass bit lines, sense amplifiers and output logic. The total signal path for an access is often a bottleneck when operating at very high speed. In burst mode, however, the delay resulting from decoding and bit cell accesses is eliminated. The present disclosure relates to further improvements of burst accesses of a memory. According to a first embodiment a burst access memory comprises: a memory array comprising a plurality of memory macros, each memory macro comprising an array of memory cells arranged in rows and columns; wherein the memory cells in each column are connected by at least one local bit line, said array of memory cells and the local bit lines defining the memory macro;a plurality of global bit lines and bit line switches, wherein each global bit line is connectable to several corresponding local bit lines of the memory macrosa controller configured to schedule a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros, wherein the plurality of macro accesses are scheduled to start with a predefined delay in relation to each other, wherein each macro access is divided into a plurality of ordered sub-operations, and wherein consecutive macro accesses are directed to different memory macros and different columns, wherein data for consecutive macro accesses are arranged in the different memory macros and the different columns to match the consecutive macro accesses. A new macro access may be scheduled to start on every clock cycle of a clock signal, and, preferably, the plurality of ordered sub-operations are executed in series, wherein each sub-operation starts on every cycle of the clock signal. The ‘clock cycle’ in this context may be seen as a reference clock or system clock. As would be understood by a person skilled in the art, if there are other clock signals running on different frequencies, each sub-operation does not necessarily have to start on every cycle. As an example, if the system clock runs at 5 GHz and a second faster clock runs at 10 GHz, the sub-operations can start at every second clock cycle of the 10 GHz clock. It is al