US-20260128089-A1 - STORAGE CIRCUITRY FOR READ AND WRITE OPERATIONS

Abstract

Storage circuitry devices, systems, and methods including a bitcell array having a plurality of bitcells, each bitcell accessible via a bitline and wordline, where the bitcell array is provided at a first layer of the storage circuitry; a redundant array associated with the bitcell array, the redundant array having a plurality of redundant bitcells, each redundant bitcell accessed via a redundant bitline and redundant wordline, where the bitcell array is provided at a second layer of the storage circuitry.

Inventors

• Kedhar Malla
• Navin Agarwal
• Rajiv Kumar Sisodia
• Sunil KUMAR KROVI
• Abhishek Kumar Singh
• Sumant KUMAR THAPLIYAL

Assignees

• ARM LIMITED

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . Storage circuitry comprising: a bitcell array having a plurality of bitcells, each bitcell accessible via at least one bitline and at least one wordline, where the bitcell array is provided at a first layer of the storage circuitry; a redundant array associated with the bitcell array, the redundant array having a plurality of redundant bitcells, each redundant bitcell accessed via at least one redundant bitline and at least one redundant wordline, where the bitcell array is provided at a second layer of the storage circuitry.
2. 2 . The storage circuitry of claim 1 , further comprising column selection circuitry to, responsive to a column select signal, select at least one bitcell via the least one bitline, where the at least one bitline comprises a first bitline portion provided at the first layer of the storage circuitry and a second bitline portion provided at the second or third layer of the storage circuitry, and where the first bitline portion is in electrical communication with the second bitline portion.
3. 3 . The storage circuitry of claim 1 , where the column selection circuitry is to, responsive to a redundant column select signal, select at least one redundant bitcell via at least one floating bitline.
4. 4 . The storage circuitry of claim 1 , where the storage circuitry comprises a floating bitline cell provided between the bitcell array and the associated redundant array.
5. 5 . The storage circuitry of claim 4 , where the first bitline portion is in electrical communication with the second bitline portion at a transition region.
6. 6 . The storage circuitry of claim 5 , where the transition region comprises a floating bitline cell.
7. 7 . The storage circuity of claim 1 , further comprising wordline selection circuitry to generate a wordline signal to select at least one bitcell.
8. 8 . The storage circuity of claim 1 , further comprising redundant row wordline selection circuitry to generate a redundant wordline signal to select at least one redundant bitcell.
9. 9 . The storage circuitry of claim 8 , where the redundant row wordline selection circuitry is to receive a faulty row address and a main address of at least one bitcell to be accessed in a read or write operation, and to determine whether there is a match between the faulty row address and the main address.
10. 10 . The storage circuitry of claim 9 , wherein, the redundant row wordline selection circuitry is to generate a match signal responsive to a match between the faulty row address and the main address.
11. 11 . The storage circuity of claim 10 , where the redundant row wordline selection circuitry is to generate the match signal responsive to a match between the faulty row address and the main address when a row redundancy enable signal is asserted.
12. 12 . The storage circuitry of claim 9 , wherein the redundant row wordline selection circuitry comprises redundant wordline driver circuitry to generate the redundant wordline signal responsive to the match signal and a clock path signal.
13. 13 . The storage circuitry of claim 3 , where the column selection circuitry comprises a column write device arranged between the second bitline portion and write driver circuitry to enable the write driver circuitry to store a data value at one or more accessed bitcells.
14. 14 . The storage circuitry of claim 3 , where the column selection circuitry comprises one or more redundant column write device arranged between the redundant bitline and write driver circuitry to enable the write driver circuitry to store a data value at one or more accessed redundant bitcells.
15. 15 . The storage circuitry of claim 14 , where a redundant column write device comprises a pass-gate to provide a word data signal to the one or more accessed bitcells.
16. 16 . The storage circuitry of claim 3 , where the column selection circuitry comprises a column read device arranged between the second bitline portion and sense amplifier circuitry.
17. 17 . The storage circuitry of claim 16 , where a redundant column read device comprises a pass-gate to enable the sense amplifier circuitry to sense a data value stored at one or more accessed bitcells.
18. 18 . The storage circuitry of claim 3 , where the redundant bitlines are electrically coupled to a common pass-gate to select one or more columns of redundant bitcells.
19. 19 . A method of controlling a read or write operation at storage circuitry comprising a bitcell array having a plurality of bitcells, each bitcell accessible via a bitline and wordline, where the bitcell array is provided at a first layer of the storage circuitry and a redundant array associated with the bitcell array, the redundant array having a plurality of redundant bitcells, each redundant bitcell accessed via a redundant bitline and redundant wordline, where the bitcell array is provided at a second layer of the storage circuitry.
20. 20 . A non-transitory computer-readable medium to store computer-readable code for fabrication of the storage circuit of claim 1 .

Description

TECHNICAL FIELD The present techniques relate to a storage system (or device) and circuitry (or circuits) therefor and particularly, but not exclusively, to row redundancy architectures for use within such systems and circuitry. BACKGROUND Conventional storage systems, such as static random access memory (SRAM) systems provide redundant rows within arrays of storage cells (bitcells). In this way, should a defect arise which renders a row inoperative, then one of the redundant rows may be functionally substituted for the row in which the defect has arisen. Conventional row redundancy mechanisms represent an additional overhead in terms of circuit area, power consumption, complexity, and timing which has to be carried by every integrated circuit irrespective of whether or not the redundancy mechanisms for that integrated circuit are needed within the particular instance. SUMMARY The present techniques relate to improving row redundancy mechanisms. According to a first aspect of present techniques there is provided storage circuitry comprising: a bitcell array having a plurality of bitcells, each bitcell accessible via at least one bitline and at least one wordline, where the bitcell array is provided at a first layer of the storage circuitry; a redundant array associated with the bitcell array, the redundant array having a plurality of redundant bitcells, each redundant bitcell accessed via at least one redundant bitline and at least one redundant wordline, where the bitcell array is provided at a second layer of the storage circuitry. According to a further aspect of present techniques, there is provided a method of controlling a read or write operation at storage circuitry comprising a bitcell array having a plurality of bitcells, each bitcell accessible via a bitline and wordline, where the bitcell array is provided at a first layer of the storage circuitry and a redundant array associated with the bitcell array, the redundant array having a plurality of redundant bitcells, each redundant bitcell accessed via a redundant bitline and redundant wordline, where the bitcell array is provided at a second layer of the storage circuitry. According to a further aspect of present techniques, there is provided a non-transitory computer-readable medium to store computer-readable code for fabrication of any circuitry described herein. BRIEF DESCRIPTION OF THE DRAWINGS Various embodiments using the present techniques will now be described by way of example only and with reference to the accompanying drawings in which: FIG. 1a shows a block level diagram of conventional storage circuitry; FIG. 1b shows a portion of the conventional storage circuitry of FIG. 1 in greater detail; FIG. 2 shows a block level diagram of a portion of storage circuitry in accordance with the present techniques; FIG. 3a shows a portion of the storage circuitry of FIG. 2 in more detail in accordance with an embodiment of the present techniques. FIG. 3b shows a portion of the storage circuitry of FIG. 3a in more detail in accordance with an embodiment of the present techniques; FIG. 4 shows a portion of the storage circuitry of FIG. 2 in accordance with a further embodiment of the present techniques; FIG. 5 shows an example embodiment of redundant row address circuitry of the storage circuitry of FIG. 2; FIG. 6a shows a waveform diagram for a read operation performed at the storage circuitry of FIG. 2; FIG. 6b shows a waveform diagram for a write operation performed at the storage circuitry of FIG. 2; FIG. 7a shows an example of write signal generation logic in accordance with the present techniques; FIG. 7b shows an example of fault write signal generation logic in accordance with the present techniques FIG. 7c shows an example of read signal generation logic in accordance with the present techniques; FIG. 7d shows an example of fault read signal generation logic in accordance with the present techniques; and FIG. 8 illustrates a process flow diagram for a manufacturing operation for fabricating storage circuitry in accordance with the present techniques. Details of methods, apparatuses, and processors according to examples will become apparent from the following description, with reference to the Figures. In this description, for the purpose of explanation, numerous specific details of certain examples are set forth. Reference in the specification to ‘an example’ or similar language means that a particular feature, structure, or characteristic described in connection with the example is included in at least that one example, but not necessarily in other examples. It should further be noted that certain examples are described schematically with certain features omitted and/or necessarily simplified for ease of explanation and understanding of the concepts underlying the examples. DETAILED DESCRIPTION Integrated circuits (ICs) include structures formed of layers where each layer may comprise polysilicon gate material in various regions and sequen