US-20260128090-A1 - MULTI-PORT STATIC RANDOM ACCESS MEMORY CELL HAVING WRITE WORD LINE OR READ WORD LINE ASSERTED MORE THAN ONCE DURING ONE CLOCK CYCLE AND ASSOCIATED STATIC RANDOM ACCESS MEMORY WITH MULTI-PORT STATIC RANDOM ACCESS MEMORY CELLS

Abstract

A multi-port static random access memory (SRAM) cell includes a storage circuit, a plurality of write port circuits, and a plurality of read port circuits. The storage circuit is used to store one bit. The write port circuits are coupled to a first node of the storage circuit. Each of the write port circuits is coupled to a write word line (WWL) and a write bit line (WBL). The read port circuits are coupled to a second node of the storage circuit. Each of the read port circuits is coupled to a read word line (RWL) and a read bit line (RBL). The WWL or the RWL is asserted more than once during a clock cycle of a clock.

Inventors

• Chi-Hao Hong

Assignees

• MEDIATEK INC.

Dates

Publication Date

20260507

Application Date

20251022

Claims (17)

1. 1 . A multi-port static random access memory (SRAM) cell comprising: a storage circuit, configured to store one bit; a plurality of write port circuits, coupled to a first node of the storage circuit, wherein each of the plurality of write port circuits is coupled to a write word line (WWL) and a write bit line (WBL); and a plurality of read port circuits, coupled to a second node of the storage circuit, wherein each of the plurality of read port circuits is coupled to a read word line (RWL) and a read bit line (RBL); wherein the WWL or the RWL is asserted more than once during a clock cycle of a clock.
2. 2 . The multi-port SRAM cell of claim 1 , wherein the WWL is asserted twice during the clock cycle.
3. 3 . The multi-port SRAM cell of claim 1 , wherein the RWL is asserted twice during the clock cycle.
4. 4 . The multi-port SRAM cell of claim 1 , wherein each of the plurality of write port circuits comprises: an inverter circuit, having an input node and an output node; and a transmission gate, comprising: a first metal-oxide-semiconductor (MOS) transistor, having a control terminal, a first connection terminal, and a second connection terminal; and a second MOS transistor, having a control terminal, a first connection terminal, and a second connection terminal; wherein the input node of the inverter circuit is coupled to the WWL and the control terminal of the first MOS transistor, the output node of the inverter circuit is coupled to the control terminal of the second MOS transistor, the first connection terminal of the first MOS transistor and the first connection terminal of the second MOS transistor are coupled to the WBL, and the second connection terminal of the first MOS transistor and the second connection terminal of the second MOS transistor are coupled to the first node of the storage circuit.
5. 5 . The multi-port SRAM cell of claim 1 , wherein the storage circuit is a feedback latch circuit with a feedback loop, the plurality of write port circuits are coupled to a plurality of WWLs, respectively, and the multi-port SRAM cell further comprises: a logic circuit, having a plurality of input nodes coupled to the plurality of WWLs, respectively, wherein the logic circuit is configured to generate at least one control signal which determines whether to cut off the feedback loop.
6. 6 . A static random access memory (SRAM) comprising: a memory array, comprising: a plurality of SRAM cells, each comprising: a storage circuit, configured to store one bit; a plurality of write port circuits, coupled to a first node of the storage circuit, wherein each of the plurality of write port circuits is coupled to a write word line (WWL) and a write bit line (WBL); and a plurality of read port circuits, coupled to a second node of the storage circuit, wherein each of the plurality of read port circuits is coupled to a read word line (RWL) and a read bit line (RBL); and a peripheral circuit, configured to control access of the plurality of SRAM cells in the memory array; wherein the WWL or the RWL is asserted more than once during a clock cycle of a clock.
7. 7 . The SRAM of claim 6 , wherein the WWL is asserted twice during the clock cycle.
8. 8 . The SRAM of claim 7 , wherein the peripheral circuit comprises: a plurality of data-in (DI) circuits, coupled to the plurality of write port circuits, respectively, wherein each of the plurality of DI circuits includes: a first digital circuit, configured to store a first bit to be provided to a write port circuit; a second digital circuit, configured to store a second bit to be provided to the write port circuit; and a multiplexer circuit, having a first input node, a second input node, and an output node, wherein the first input node is coupled to the first digital circuit, the second input node is coupled to the second digital circuit, and the output node is configured to output the first bit during a first phase of the clock cycle and output the second bit during a second phase of the clock cycle.
9. 9 . The SRAM of claim 8 , wherein the first digital circuit and the second digital circuit are both triggered by a rising edge of the clock.
10. 10 . The SRAM of claim 8 , wherein the first digital circuit is triggered by a rising edge of the clock, and the second digital circuit is triggered by a falling edge of the clock.
11. 11 . The SRAM of claim 8 , wherein the first digital circuit is a latch circuit, and the second digital circuit is a D-type flip-flop (DFF) circuit.
12. 12 . The SRAM of claim 8 , wherein both of the first digital circuit and the second digital circuit are latch circuits.
13. 13 . The SRAM of claim 6 , wherein the RWL is asserted twice during the clock cycle.
14. 14 . The SRAM of claim 13 , wherein the peripheral circuit comprises: a plurality of data-out (DO) circuits, coupled to the plurality of read port circuits, respectively, wherein each of the plurality of DO circuits includes: a first digital circuit, configured to store one bit output from a read port circuit during a first phase of the clock cycle; and a second digital circuit, configured to store one bit output from the read port circuit during a second phase of the clock cycle.
15. 15 . The SRAM of claim 14 , wherein both of the first digital circuit and the second digital circuit are latch circuits.
16. 16 . The SRAM of claim 14 , wherein the first digital circuit is a latch circuit, and the second digital circuit is a D-type flip-flop (DFF) circuit.
17. 17 . The SRAM of claim 14 , wherein both of the first digital circuit and the second digital circuit are D-type flip-flop (DFF) circuits.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/714,866, filed on November 1st, 2024. The content of the application is incorporated herein by reference. BACKGROUND The present invention relates to a static random access memory (SRAM) design, and more particularly, to a multi-port SRAM cell having a write word line (WWL) and/or a read word line (RWL) asserted more than once during one clock cycle and an associated SRAM with multi-port SRAM cells. In high speed computers and digital signal processors, multiport SRAMs are essential components, especially in modern multi-core system on a chip (SoC). For example, a conventional multi-port SRAM cell that allows simultaneous N read operations/M write operations is required to have N read ports and M write ports. When the numbers of read ports and write ports are increased to meet requirements of high speed applications, a conventional SRAM with multi-port SRAM cells requires a larger die area, which increases the area and the power consumption of the SOC. Thus, there is a need for an innovative multi-port SRAM cell design which provides simultaneous N read operations by using N’ (N’ < N) read ports and provides simultaneous M write operations by using M’ (M’ < M) write ports. SUMMARY One of the objectives of the claimed invention is to provide a multi-port SRAM cell having a WWL and/or an RWL asserted more than once during one clock cycle and an associated SRAM with multi-port SRAM cells. According to a first aspect of the present invention, an exemplary multi-port static random access memory (SRAM) cell is disclosed. The exemplary multi-port SRAM cell includes a storage circuit, a plurality of write port circuits, and a plurality of read port circuits. The storage circuit is configured to store one bit. The write port circuits are coupled to a first node of the storage circuit. Each of the write port circuits is coupled to a write word line (WWL) and a write bit line (WBL). The read port circuits are coupled to a second node of the storage circuit. Each of the read port circuits is coupled to a read word line (RWL) and a read bit line (RBL). The WWL or the RWL is asserted more than once during a clock cycle of a clock. According to a second aspect of the present invention, an exemplary static random access memory (SRAM) is disclosed. The exemplary SRAM includes a memory array and a peripheral circuit. The memory array includes a plurality of SRAM cells, each having a storage circuit, a plurality of write port circuits, and a plurality of read port circuits. The storage circuit is configured to store one bit. The write port circuits are coupled to a first node of the storage circuit. Each of the write port circuits is coupled to a write word line (WWL) and a write bit line (WBL). The read port circuits are coupled to a second node of the storage circuit. Each of the read port circuits is coupled to a read word line (RWL) and a read bit line (RBL). The peripheral circuit is configured to control access of the plurality of SRAM cells in the memory array. The WWL or the RWL is asserted more than once during a clock cycle of a clock. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating an SRAM design according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a multi-port SRAM cell design according to an embodiment of the present invention. FIG. 3 is a diagram illustrating waveforms of WWL signals and RWL signals used by a double-pumped 4R4W multiport-SRAM cell according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a DI circuit design according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a DO circuit design according to an embodiment of the present invention. DETAILED DESCRIPTION Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to ...". Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. FIG. 1 is a diagram illustrating an SRAM design according to an